High-performance image acquisition and processing system with MTCA.4

Author(s):  
D. Makowski ◽  
A. Mielczarek ◽  
P. Perek ◽  
G. Jablonski ◽  
M. Orlikowski ◽  
...  
2011 ◽  
Vol 128-129 ◽  
pp. 1480-1483
Author(s):  
Kai Song ◽  
Zhe Wang ◽  
Feng Ju Shen

The crop leaf disease spots image recognition technology has a great significance in identifying diseases and in effective spraying of pesticides to liminate diseases. We researched and designed the portable leaf disease spots image acquisition system since current PC-based processing system is high cost and lack of flexibility and real-timing, This system uses a high-performance 32-bit DSP chip based DM642 as its main processor, and also uses ultra-low power consumption and ultra-small size video decoder chips, large-capacity memories and high-performance communicator interfaces. As a result of the reasonable design of hardware architecture, this system realized leaf disease spots image features collecting and processing ,video transmitting, and achieved strong real-time processing capability, easy operation, low cost, anti-interference ability and other characteristics. The system prototype works well, and meets the design requirements.


2012 ◽  
Vol 433-440 ◽  
pp. 5482-5488 ◽  
Author(s):  
Su Ran Kong

Image processing system to calculate the volume, real-time high and the requirements of small size, using the DSP-based processor, FPGA approach, supplemented by the processor design of a high-performance real-time image processing system, and the system In the process of image acquisition and transmission of noise, using the PCB's anti-jamming design. Practice shows that two chips using FPGA + DSP, the algorithm is divided into two parts by the FPGA and DSP processing; effectively improve the efficiency of the algorithm. System real-time high, adaptability, real-time image acquisition system can meet the design requirements.


2013 ◽  
Vol 401-403 ◽  
pp. 1507-1513 ◽  
Author(s):  
Zhong Hu Yuan ◽  
Wen Tao Liu ◽  
Xiao Wei Han

In the weld image acquisition system, real-time image processing has been a difficult design bottleneck to break through, especially for the occasion of large data processing capability and more demanding real-time requirements, in which the traditional MCU can not adapt, so using high-performance FPGA as the core of the high speed image acquisition and processing card, better meets the large amount of data in most of the image processing system and high demanding real-time requirements. At the same time, system data collection, storage and display were implemented by using Verilog, and in order to reducing the influence of edge detection noise, the combination of image enhancement and median filtering image preprocessing algorithm was used. Compared to the pre-processing algorithm of the software implementation, it has a great speed advantage, and simplifies the subsequent processing work load, improves the speed and efficiency of the entire image processing system greatly. So it proves that the system has strong ability of restraining the noise of image, and more accurate extracted edge positioning, it can be applied in the seam tracking field which need higher real-time requirements.


2015 ◽  
Vol 62 (3) ◽  
pp. 925-931 ◽  
Author(s):  
D. Makowski ◽  
A. Mielczarek ◽  
P. Perek ◽  
G. Jablonski ◽  
M. Orlikowski ◽  
...  

2021 ◽  
Vol 13 (3) ◽  
pp. 78
Author(s):  
Chuanhong Li ◽  
Lei Song ◽  
Xuewen Zeng

The continuous increase in network traffic has sharply increased the demand for high-performance packet processing systems. For a high-performance packet processing system based on multi-core processors, the packet scheduling algorithm is critical because of the significant role it plays in load distribution, which is related to system throughput, attracting intensive research attention. However, it is not an easy task since the canonical flow-level packet scheduling algorithm is vulnerable to traffic locality, while the packet-level packet scheduling algorithm fails to maintain cache affinity. In this paper, we propose an adaptive throughput-first packet scheduling algorithm for DPDK-based packet processing systems. Combined with the feature of DPDK burst-oriented packet receiving and transmitting, we propose using Subflow as the scheduling unit and the adjustment unit making the proposed algorithm not only maintain the advantages of flow-level packet scheduling algorithms when the adjustment does not happen but also avoid packet loss as much as possible when the target core may be overloaded Experimental results show that the proposed method outperforms Round-Robin, HRW (High Random Weight), and CRC32 on system throughput and packet loss rate.


2021 ◽  
Vol 49 (4) ◽  
pp. 12-17
Author(s):  
Feilong Liu ◽  
Claude Barthels ◽  
Spyros Blanas ◽  
Hideaki Kimura ◽  
Garret Swart

Networkswith Remote DirectMemoryAccess (RDMA) support are becoming increasingly common. RDMA, however, offers a limited programming interface to remote memory that consists of read, write and atomic operations. With RDMA alone, completing the most basic operations on remote data structures often requires multiple round-trips over the network. Data-intensive systems strongly desire higher-level communication abstractions that supportmore complex interaction patterns. A natural candidate to consider is MPI, the de facto standard for developing high-performance applications in the HPC community. This paper critically evaluates the communication primitives of MPI and shows that using MPI in the context of a data processing system comes with its own set of insurmountable challenges. Based on this analysis, we propose a new communication abstraction named RDMO, or Remote DirectMemory Operation, that dispatches a short sequence of reads, writes and atomic operations to remote memory and executes them in a single round-trip.


2014 ◽  
Vol 28 (07) ◽  
pp. 1450056 ◽  
Author(s):  
Hua-Lin Cai ◽  
Yi Yang ◽  
Yi-Han Zhang ◽  
Chang-Jian Zhou ◽  
Cang-Ran Guo ◽  
...  

In this paper, a surface acoustic wave (SAW) biosensor with gold delay area on LiNbO 3 substrate detecting DNA sequences is proposed. By well-designed device parameters of the SAW sensor, it achieves a high performance for highly sensitive detection of target DNA. In addition, an effective biological treatment method for DNA immobilization and abundant experimental verification of the sensing effect have made it a reliable device in DNA detection. The loading mass of the probe and target DNA sequences is obtained from the frequency shifts, which are big enough in this work due to an effective biological treatment. The experimental results show that the biosensor has a high sensitivity of 1.2 pg/ml/Hz and high selectivity characteristic is also verified by the few responses of other substances. In combination with wireless transceiver, we develop a wireless receiving and processing system that can directly display the detection results.


2014 ◽  
Vol 687-691 ◽  
pp. 3733-3737
Author(s):  
Dan Wu ◽  
Ming Quan Zhou ◽  
Rong Fang Bie

Massive image processing technology requires high requirements of processor and memory, and it needs to adopt high performance of processor and the large capacity memory. While the single or single core processing and traditional memory can’t satisfy the need of image processing. This paper introduces the cloud computing function into the massive image processing system. Through the cloud computing function it expands the virtual space of the system, saves computer resources and improves the efficiency of image processing. The system processor uses multi-core DSP parallel processor, and develops visualization parameter setting window and output results using VC software settings. Through simulation calculation we get the image processing speed curve and the system image adaptive curve. It provides the technical reference for the design of large-scale image processing system.


2011 ◽  
Vol 383-390 ◽  
pp. 471-475
Author(s):  
Yong Bin Hong ◽  
Cheng Fa Xu ◽  
Mei Guo Gao ◽  
Li Zhi Zhao

A radar signal processing system characterizing high instantaneous dynamic range and low system latency is designed based on a specifically developed signal processing platform. Instantaneous dynamic range loss is a critical problem when digital signal processing is performed on fixed-point FPGAs. In this paper, the problem is well resolved by increasing the wordlength according to signal-to-noise ratio (SNR) gain of the algorithms through the data path. The distinctive software structure featuring parallel pipelined processing and “data flow drive” reduces the system latency to one coherent processing interval (CPI), which significantly improves the maximum tracking angular velocity of the monopulse tracking radar. Additionally, some important electronic counter-countermeasures (ECCM) are incorporated into this signal processing system.


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