scholarly journals Hardware architecture design and implementation of ray-triangle intersection with bounding volume hierarchies

2008 ◽  
Author(s):  
Chen-Haur Chang ◽  
Chuan-Yiu Lee ◽  
Shao-Yi Chien
Keyword(s):  
Hardware Architecture ◽  
Architecture Design ◽  
Design And Implementation ◽  
Bounding Volume ◽  
Bounding Volume Hierarchies

Bounding Volume Hierarchies for Detecting Collision in Urban Simulation

2008 ◽  
Author(s):  
Hamzah Asyrani Sulaiman ◽  
Abdullah Bade ◽  
Daut Daman ◽  
Mohd Shahrizal Sunar
Keyword(s):  
Bounding Volume ◽  
Urban Simulation ◽  
Bounding Volume Hierarchies

A Survey on Bounding Volume Hierarchies for Ray Tracing

2021 ◽  
Vol 40 (2) ◽  
pp. 683-712
Author(s):  
Daniel Meister ◽  
Shinji Ogaki ◽  
Carsten Benthin ◽  
Michael J. Doyle ◽  
Michael Guthe ◽  
...  
Keyword(s):  
Ray Tracing ◽  
Bounding Volume ◽  
Bounding Volume Hierarchies

Hardware-Accelerated Dual-Split Trees

2020 ◽  
Vol 3 (2) ◽  
pp. 1-21
Author(s):  
Daqi Lin ◽  
Elena Vasiou ◽  
Cem Yuksel ◽  
Daniel Kopta ◽  
Erik Brunvand
Keyword(s):  
Ray Tracing ◽  
Hardware Acceleration ◽  
Memory Storage ◽  
Compact Representation ◽  
Space Partitioning ◽  
Data Movement ◽  
Bounding Volume ◽  
Bounding Boxes ◽  
Split Trees ◽  
Bounding Volume Hierarchies

Bounding volume hierarchies (BVH) are the most widely used acceleration structures for ray tracing due to their high construction and traversal performance. However, the bounding planes shared between parent and children bounding boxes is an inherent storage redundancy that limits further improvement in performance due to the memory cost of reading these redundant planes. Dual-split trees can create identical space partitioning as BVHs, but in a compact form using less memory by eliminating the redundancies of the BVH structure representation. This reduction in memory storage and data movement translates to faster ray traversal and better energy efficiency. Yet, the performance benefits of dual-split trees are undermined by the processing required to extract the necessary information from their compact representation. This involves bit manipulations and branching instructions which are inefficient in software. We introduce hardware acceleration for dual-split trees and show that the performance advantages over BVHs are emphasized in a hardware ray tracing context that can take advantage of such acceleration. We provide details on how the operations needed for decoding dual-split tree nodes can be implemented in hardware and present experiments in a number of scenes with different sizes using path tracing. In our experiments, we have observed up to 31% reduction in render time and 38% energy saving using dual-split trees as compared to binary BVHs representing identical space partitioning.

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