High-Level System Modeling for Rapid HW/SW Architecture Exploration

2009 ◽  
Author(s):  
Chafic Jaber ◽  
Andreas Kanstein ◽  
Ludovic Apvrille ◽  
Amer Baghdadi ◽  
Patricia Le Moënner ◽  
...  
Keyword(s):  
System Modeling ◽  
Level System ◽  
Architecture Exploration ◽  
High Level

scholarly journals An ESL Approach for Energy Consumption Analysis of Cache Memories in SoC Platforms

2011 ◽  
Vol 2011 ◽  
pp. 1-12 ◽  
Author(s):  
Abel G. Silva-Filho ◽  
Filipe R. Cordeiro ◽  
Cristiano C. Araújo ◽  
Adriano Sarmento ◽  
Millena Gomes ◽  
...  
Keyword(s):  
Energy Consumption ◽  
System Modeling ◽  
Electronic System ◽  
System Level ◽  
Energy Consumption Analysis ◽  
Electronic System Level ◽  
Architecture Exploration ◽  
Uml 2.0 ◽  
Complex Circuits ◽  
High Level

The design of complex circuits as SoCs presents two great challenges to designers. One is the speeding up of system functionality modeling and the second is the implementation of the system in an architecture that meets performance and power consumption requirements. Thus, developing new high-level specification mechanisms for the reduction of the design effort with automatic architecture exploration is a necessity. This paper proposes an Electronic-System-Level (ESL) approach for system modeling and cache energy consumption analysis of SoCs called PCacheEnergyAnalyzer. It uses as entry a high-level UML-2.0 profile model of the system and it generates a simulation model of a multicore platform that can be analyzed for cache tuning. PCacheEnergyAnalyzer performs static/dynamic energy consumption analysis of caches on platforms that may have different processors. Architecture exploration is achieved by letting designers choose different processors for platform generation and different mechanisms for cache optimization. PCacheEnergyAnalyzer has been validated with several applications of Mibench, Mediabench, and PowerStone benchmarks, and results show that it provides analysis with reduced simulation effort.

High Level System-on-Chip Design using UML and SystemC

2007 ◽  
Author(s):  
Blanca Alicia Correa ◽  
Juan Fernando Eusse ◽  
Danny Munera ◽  
Jose Edinson Aedo ◽  
Juan Fernando Velez
Keyword(s):  
System On Chip ◽  
Level System ◽  
Chip Design ◽  
On Chip ◽  
High Level

Modelling high level system design and unit commitment for a microgrid

2009 ◽  
Vol 86 (7-8) ◽  
pp. 1253-1265 ◽  
Author(s):  
A.D. Hawkes ◽  
M.A. Leach
Keyword(s):  
System Design ◽  
Unit Commitment ◽  
Level System ◽  
High Level

From MARTE to Reconfigurable NoCs

2010 ◽  
pp. 135-157
Author(s):  
Imran Rafiq Quadri ◽  
Majdi Elhaji ◽  
Samy Meftali ◽  
Jean-Luc Dekeyser
Keyword(s):  
System Modeling ◽  
Unified Modeling Language ◽  
Modeling And Analysis ◽  
Unified Modeling ◽  
Model Driven ◽  
Abstraction Level ◽  
Management Group ◽  
High Level Modeling ◽  
High Level ◽  
Abstraction Levels

Due to the continuous exponential rise in SoC’s design complexity, there is a critical need to find new seamless methodologies and tools to handle the SoC co-design aspects. We address this issue and propose a novel SoC co-design methodology based on Model Driven Engineering and the MARTE (Modeling and Analysis of Real-Time and Embedded Systems) standard proposed by Object Management Group, to raise the design abstraction levels. Extensions of this standard have enabled us to move from high level specifications to execution platforms such as reconfigurable FPGAs. In this chapter, we present a high level modeling approach that targets modern Network on Chips systems. The overall objective: to perform system modeling at a high abstraction level expressed in Unified Modeling Language (UML); and afterwards, transform these high level models into detailed enriched lower level models in order to automatically generate the necessary code for final FPGA synthesis.

Architectural Modelling of Cyber Physical Systems Using UML

2019 ◽  
Vol 1 (2) ◽  
pp. 19-37
Author(s):  
K. Sridhar Patnaik ◽  
Itu Snigdh
Keyword(s):  
System Modeling ◽  
Unified Modeling Language ◽  
Research Area ◽  
Cyber Physical Systems ◽  
Engineering Systems ◽  
Physical Systems ◽  
Unified Modeling ◽  
System Verification ◽  
High Level ◽  
Modeling Representation

Cyber-physical systems (CPS) is an exciting emerging research area that has drawn the attention of many researchers. However, the difficulties of computing and physical paradigm introduce a lot of trials while developing CPS, such as incorporation of heterogeneous physical entities, system verification, security assurance, and so on. A common or unified architecture plays an important role in the process of CPS design. This article introduces the architectural modeling representation of CPS. The layers of models are integrated from high level to lower level to get the general Meta model. Architecture captures the essential attributes of a CPS. Despite the rapid growth in IoT and CPS a general principled modeling approach for the systematic development of these new engineering systems is still missing. System modeling is one of the important aspects of developing abstract models of a system wherein, each model represents a different view or perspective of that system. With Unified Modeling Language (UML), the graphical analogy of such complex systems can be successfully presented.

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