Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors

18th IEEE/IFIP International Workshop on Rapid System Prototyping (RSP '07) ◽

10.1109/rsp.2007.32 ◽

2007 ◽

Cited By ~ 1

Author(s):

A. Chattopadhyay ◽

Z. Rakosi ◽

K. Karuri ◽

D. Kammler ◽

R. Leupers ◽

...

Keyword(s):

Vliw Processors ◽

Architecture Exploration

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Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors

ACM Transactions on Embedded Computing Systems ◽

10.1145/1376804.1376808 ◽

2008 ◽

Vol 7 (4) ◽

pp. 1-31 ◽

Cited By ~ 2

Author(s):

A. Chattopadhyay ◽

H. Ishebabi ◽

X. Chen ◽

Z. Rakosi ◽

K. Karuri ◽

...

Keyword(s):

Vliw Processors ◽

Architecture Exploration

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A Fast Architecture Exploration Method for High Throughput IEEE 802.11e MAC Implementation Using SystemC

IEICE Transactions on Communications ◽

10.1587/transcom.e93.b.2833 ◽

2010 ◽

Vol E93-B (10) ◽

pp. 2833-2836

Author(s):

Sung-Rok YOON ◽

Min Li HUANG ◽

Sangho SEO ◽

Hiroshi OCHI ◽

Sin-Chong PARK

Keyword(s):

High Throughput ◽

Ieee 802.11E ◽

Architecture Exploration

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Architecture exploration for ambient energy harvesting nonvolatile processors

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA) ◽

10.1109/hpca.2015.7056060 ◽

2015 ◽

Cited By ~ 110

Author(s):

Kaisheng Ma ◽

Yang Zheng ◽

Shuangchen Li ◽

Karthik Swaminathan ◽

Xueqing Li ◽

...

Keyword(s):

Energy Harvesting ◽

Architecture Exploration

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Branch prediction techniques for low-power VLIW processors

Proceedings of the 13th ACM Great Lakes Symposium on VLSI - GLSVLSI '03 ◽

10.1145/764808.764866 ◽

2003 ◽

Cited By ~ 7

Author(s):

G. Palermo ◽

M. Sam ◽

C. Silvan ◽

V. Zaccari ◽

R. Zafalo

Keyword(s):

Low Power ◽

Branch Prediction ◽

Vliw Processors ◽

Prediction Techniques

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Single-chip multi-processor integrating quadruple 8-way vliw processors with interface timing analysis considering power supply noise

Asia and South Pacific Conference on Design Automation, 2006. ◽

10.1109/aspdac.2006.1594741 ◽

2006 ◽

Author(s):

S. Imai ◽

A. Inoue ◽

M. Matsumura ◽

K. Kawasaki ◽

A. Suga

Keyword(s):

Power Supply ◽

Timing Analysis ◽

Power Supply Noise ◽

Single Chip ◽

Vliw Processors ◽

Supply Noise

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Architecture Exploration for a Reconfigurable Architecture Template

IEEE Design & Test of Computers ◽

10.1109/mdt.2005.27 ◽

2005 ◽

Vol 22 (2) ◽

pp. 90-101 ◽

Cited By ~ 96

Author(s):

Bingfeng Mei ◽

A. Lambrechts ◽

D. Verkest ◽

J. Mignolet ◽

R. Lauwereins

Keyword(s):

Reconfigurable Architecture ◽

Architecture Exploration

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On the Statistical Memory Architecture Exploration and Optimization

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015 ◽

10.7873/date.2015.0839 ◽

2015 ◽

Cited By ~ 1

Author(s):

Charalampos Antoniadis ◽

Georgios Karakonstantis ◽

Nestor Evmorfopoulos ◽

Andreas Burg ◽

George Stamoulis

Keyword(s):

Memory Architecture ◽

Architecture Exploration

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An efficient heuristic for instruction scheduling on clustered vliw processors

Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems - CASES '11 ◽

10.1145/2038698.2038707 ◽

2011 ◽

Cited By ~ 5

Author(s):

Xuemeng Zhang ◽

Hui Wu ◽

Jingling Xue

Keyword(s):

Instruction Scheduling ◽

Vliw Processors

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Hardware Architecture Exploration for Deep Neural Networks

Arabian Journal for Science and Engineering ◽

10.1007/s13369-021-05455-4 ◽

2021 ◽

Author(s):

Wenqi Zheng ◽

Yangyi Zhao ◽

Yunfan Chen ◽

Jinhong Park ◽

Hyunchul Shin

Keyword(s):

Neural Networks ◽

Deep Neural Networks ◽

Hardware Architecture ◽

Architecture Exploration

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System-Level Specification and Architecture Exploration : an Avionics Codesign Application

Electronic Chips & Systems Design Languages ◽

10.1007/978-1-4757-3326-6_9 ◽

2001 ◽

pp. 111-120

Author(s):

François Cloute ◽

Jean-Noël Contensou ◽

Daniel Esteve ◽

Pascal Pampagnin ◽

Philippe Pons ◽

...

Keyword(s):

System Level ◽

Architecture Exploration

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