Analysis of the effects of supply noise coupling on phase noise in integrated LC CMOS oscillators

2002 ◽  
Author(s):  
R. Fetche ◽  
C. Fetche ◽  
T. Fiez ◽  
K. Mayaram
Keyword(s):  
Phase Noise ◽  
Noise Coupling ◽  
Supply Noise ◽  
Cmos Oscillators

Ring Oscillator Phase Noise Properties due to PSN with Deterministic Frequency

2012 ◽  
Vol 496 ◽  
pp. 527-533
Author(s):  
Na Bai ◽  
Hong Gang Zhou ◽  
Qiu Lei Wu ◽  
Chun Yu Peng
Keyword(s):  
Phase Noise ◽  
Ring Oscillator ◽  
Cmos Process ◽  
Analysis Method ◽  
Noise Performance ◽  
Supply Noise ◽  
Total Phase ◽  
Phase Noise Performance ◽  
Oscillator Phase Noise ◽  
Oscillator Phase

In this paper, ring oscillator phase noise caused by power supply noise (PSN) with deterministic frequency is analyzed. Results show that phase noise caused by deterministic noise is only an impulse series. Compared with the jitter caused by PSN, the phase noise caused by PSN with deterministic frequency contributes considerably less to total phase noise performance. To verify the analysis method, a CMOS ring oscillator is designed and fabricated using SMIC 0.13 µm CMOS process. Comparisons between the analytical results and measurements prove the accuracy of the proposed method

Design and analysis of a low noise CMOS charge pump phase locked loop circuit

2021 ◽  
pp. 2140002
Author(s):  
Yanbo Chen ◽  
Shubin Zhang
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Low Noise ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Output Frequency ◽  
Power Supply Voltage ◽  
Supply Noise

Phase Locked Loop (PLL) circuit plays an important part in electronic communication system in providing high-frequency clock, recovering the clock from data signal and so on. The performance of PLL affects the whole system. As the frequency of PLL increases, designing a PLL circuit with lower jitter and phase noise becomes a big challenge. To suppress the phase noise, the optimization of Voltage Controlled Oscillator (VCO) is very important. As the power supply voltage degrades, the VCO becomes more sensitive to supply noise. In this work, a three-stage feedforward ring VCO (FRVCO) is designed and analyzed to increase the output frequency. A novel supply-noise sensing (SNS) circuit is proposed to suppress the supply noise’s influence on output frequency. Based on these, a 1.2 V 2 GHz PLL circuit is implemented in 110 nm CMOS process. The phase noise of this CMOS charge pump (CP) PLL is 117 dBc/Hz@1 MHz from test results which proves it works successfully in suppressing phase noise.

scholarly journals A study of phase noise in colpitts and LC-tank CMOS oscillators

2005 ◽  
Vol 40 (5) ◽  
pp. 1107-1118 ◽  
Author(s):  
P. Andreani ◽  
Xiaoyan Wang ◽  
L. Vandi ◽  
A. Fard
Keyword(s):  
Phase Noise ◽  
Cmos Oscillators ◽  
Lc Tank

scholarly journals A Practical Load-optimized VCO Design for Low-jitter 5V 500 MHz Digital Phase-locked Loop

VLSI Design ◽  
2000 ◽  
Vol 11 (2) ◽  
pp. 107-113
Author(s):  
Chua-Chin Wang ◽  
Yu-Tsun Chien ◽  
Ying-Pei Chen
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
Phase Locked Loops ◽  
Digital Cmos ◽  
Display Devices ◽  
Noise Coupling ◽  
Signal Systems ◽  
Supply Noise ◽  
Low Jitter ◽  
Rc Circuit

In high-speed digital systems and high-resolution display devices, the jitter effect of phase-locked loops (PLL) limits the system performance. Power supply noise coupling is one of the major causes of PLL jitter problems, especially with mixed-signal systems. The paper presents a targeted 5.0V 500 MHz PLL which is implemented by a 0.6 um 1P3M digital CMOS technology. The features of the proposed design include a load-optimized 3-stage VCO, a frequency limiter RC circuit, and a ratioed VCO controlling current mirror. The jitter, thus, is reduced to 72.693 ps at 600 MHz at the presence of supply noise, while the sensitivity is limited to 286.6 ps/V. This high-noise immunity design allows that the PLL can be integrated with digital circuits.

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