Accessible formal verification for safety-critical hardware design

Pacemakers are safety-critical devices whose faulty behaviors can cause harm or even death. Often these faulty behaviors are caused due to bugs in programs used for digital control of pacemakers. We present a formal verification methodology that can be used to check the correctness of object code programs that implement the safety-critical control functions of DDD mode pacemakers. Our methodology is based on the theory of Well-Founded Equivalence Bisimulation (WEB) refinement, where both formal specifications and implementation are treated as transition systems. We develop a simple and general formal specification for DDD mode pacemakers. We also develop correctness proof obligations that can be applied to validate object code programs used for pacemaker control. Using our methodology, we were able to verify a control program with millions of transitions against the simple specification with only 10 transitions. Our method also found several bugs during the verification process.

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Model Checking for SpaceWire Error Detection Module

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.241-244.3020 ◽

2012 ◽

Vol 241-244 ◽

pp. 3020-3025

Author(s):

Ling Ling Dong ◽

Yong Guan ◽

Xiao Juan Li ◽

Zhi Ping Shi ◽

Jie Zhang ◽

...

Keyword(s):

Model Checking ◽

Formal Verification ◽

Temporal Logic ◽

Error Detection ◽

System Model ◽

Linear Search ◽

Kripke Structure ◽

Mathematical Methods ◽

Safety Critical ◽

Correctness Of Programs

Considerable attention has been devoted to prove the correctness of programs. Formal verification overcomes the incompleteness by applying mathematical methods to verify a design. SpaceWire is a well known communication standard. For safety-critical applications an approach is needed to validate the completeness of SpareWire design. This paper addresses formal verification of SpareWire error detection module. The system model was constructed by Kripke structure, and the properties were presented by linear temporal logic (LTL). Compared the verification of LTL with CTL (branch temporal logic), LTL properties could improve the verification efficiency due to its linear search. The error priority was checked using simulation guided by model checking. After some properties were modified, all possible behaviors of the module satisfied the specification. This method realizes complete validation of the error detection module.

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Formal verification of safety-critical systems

Software Practice and Experience ◽

10.1002/spe.4380200804 ◽

1990 ◽

Vol 20 (8) ◽

pp. 799-821 ◽

Cited By ~ 18

Author(s):

Louise E. Moser ◽

P. M. Melliar-Smith

Keyword(s):

Formal Verification ◽

Critical Systems ◽

Safety Critical ◽

Safety Critical Systems

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A Formal Verification Method of Compilation Based on C Safety Subset

Wireless Communications and Mobile Computing ◽

10.1155/2021/8352267 ◽

2021 ◽

Vol 2021 ◽

pp. 1-10

Author(s):

Yu Tan ◽

Dianfu Ma ◽

Lei Qiao

Keyword(s):

Wireless Communication ◽

Formal Verification ◽

Communication Systems ◽

System Development ◽

Axiom System ◽

Proof Complexity ◽

Verification Method ◽

Safety Critical ◽

Algorithm Efficiency ◽

Verification Methods

With the rapid increase in the number of wireless terminals and the openness of wireless networks, the security of wireless communication is facing serious challenges. The safety and security of computer communication have always been a research hotspot, especially the wireless communication that still has a more complex architecture which leads to more safety problems in the communication system development. In recent years, more and more wireless communication systems are applied in the safety-critical field which tends to need high safety guarantees. A compiler is an important tool for system development, and its safety and reliability have an important impact on the development of safety-critical software. As the strictest method, formal verification methods have been widely paid attention to in compiler verification, but the current formal verification methods have some problems, such as high proof complexity, weak verification ability, and low algorithm efficiency. In this paper, a compiler formal verification method based on safety C subsets is proposed. By abstracting the concept of C grammar units from safety C subsets, the formal verification of the compiler is transformed into the verification of limited C grammar units. In this paper, an axiom system of first-order logic and special axioms are introduced. On this axiom system, the semantic consistency verification of C grammar unit and target code pattern is completed by means of theorem proving, and the formal verification of the compiler is completed.

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