Accelerated temperature cycle test and Coffin-Manson model for electronic packaging

2005 ◽  
Author(s):  
H. Cui
Keyword(s):  
Electronic Packaging ◽  
Temperature Cycle ◽  
Temperature Cycle Test

Development of Lead-Free Flip Chip Package and Its Reliability

2003 ◽  
Author(s):  
Jeffrey C. B. Lee ◽  
Sting Wu ◽  
H. L. Chou ◽  
Yi-Shao Lai
Keyword(s):  
Failure Mode ◽  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Wire Bonding ◽  
Point Of View ◽  
Lead Free ◽  
Temperature Cycle ◽  
Snagcu Solder ◽  
Temperature Cycle Test

SnAgCu solder used in laminate package like PBGA and CSP BGA to replace eutectic SnPb as interconnection has become major trend in the electronic industry. But unlike well-known failure mode of wire bonding package, flip chip package with SnAgCu inner solder bump and external solder ball as electrical interconnection present a extremely different failure mode with wire-bonding package from a point of view in material and process. In this study, one 16mm×16mm 3000 I/O SnAgCu wafer bumping using screen-printing process was explored including the effects of reflow times, high temperature storage life (HTSL) and temperature cycle test (TCT) on bump shear strength. Furthermore, the qualified wafer bumping is assembled by flip chip assembly with various underfill material and specific organic build-up substrate, then is subject to MSL4/260°C precondition and temperature cycle test to observe the underfill effect on SnAgCu bump protection and solder joint life. Various failure modes in the flip chip package like solder bump, underfill and UBM and so on, will be scrutinized with SEM. And finally, best material combination will be addressed to make the lead free flip package successful.

The Analysis of Some Problems of Environmental Stress Screening of Electronic Equipment

2014 ◽  
Vol 556-562 ◽  
pp. 1487-1490 ◽  
Author(s):  
Xiang Jun Song ◽  
Wan Ling Li
Keyword(s):  
Environmental Stress ◽  
Electronic Equipment ◽  
Assembly System ◽  
Temperature Cycle ◽  
Electronic Assembly ◽  
Temperature Cycle Test

This article analyses the importance of equipment environment screen (ESS), and analyses the intention, demand and trait of the ESS, and the relatives between ESS and equipment experiment. Besides, it analyses the ESS implement project of printed board, electronic assembly system under the screen of temperature cycle test and random shake environment, and draw some benefiting conclusion.

Development of thin package using the glass carrier substrate

2015 ◽  
Vol 2015 (1) ◽  
pp. 000087-000091
Author(s):  
Jun Onohara ◽  
Takashi Fujita ◽  
Yoshito Akutagawa
Keyword(s):  
Injection Molding ◽  
Adhesive Layer ◽  
Temperature Cycle ◽  
Effective Solution ◽  
Thermal Compression ◽  
Temperature Cycle Test

“The glass carrier substrate” formed on support glass using conventional build-up substrate technologies is developed. This substrate is ultrathin, and is suitable for the applications that thinner packages are highly demanded, such as for mobiles. The advantage of glass as the carrier for the substrate is that the CTE of glass is close to that of silicon. The CTE matching of glass with silicon enables the narrow pitch mounting, because of reduced distortions between the chip and the substrate. When the chip is bonded on the substrate, glass is still combined with the substrate as the carrier. After chip bonding, the substrate can easily peeled off with laser irradiating through glass due to the characters of adhesive layer. To verify the advantage, we prepared the thin substrate and made a connection with a narrow pitch (50um) bump chip, by means of Thermal Compression Bonding with non-conductive paste. The process of injection molding was used for packaging the substrate. We evaluated the reliability of the thin package, by temperature cycle test (JEDEC MSL-3+Cond.B). It was confirmed that the package passed the criteria. It is convinced that the package with glass carrier substrate is an effective solution for making thinner packages.

TCT Reliability of Organic Passivation Layer for WLCSP

2015 ◽  
Vol 2015 (1) ◽  
pp. 000505-000509 ◽  
Author(s):  
Mitsuru Fujita ◽  
Atsushi Fujii ◽  
Shuji Shimoda ◽  
Yoshiharu Kariya
Keyword(s):  
Passivation Layer ◽  
Fatigue Properties ◽  
Temperature Cycle ◽  
Wafer Level ◽  
Element Analysis ◽  
Joint Reliability ◽  
Solder Bumps ◽  
Temperature Cycle Test ◽  
Board Level ◽  
Interconnect Technology

Wafer level chip scale packages (WLCSP) have been increasingly used in portable electronic products such as mobile phones. Solder bumps with redistribution layer (RDL) are typical interconnect technology for WLCSP applications. One of the major concerns in joint reliability is the failure by temperature cyclic stresses. In addition, in terms of heat tolerance or device yields, process temperature of RDL dielectric is limited around 200deg.C in some packaging applications. According to our board level reliability test for temperature cycle test (TCT), photosensitive polyimide (PI) which is 200deg.C curable material has lower fail rate than polybenzoxazole (PBO) by TCT. In this study, we compared the actual board level test and Finite Element Analysis (FEA) during temperature cycle test, and correlated the mechanical and fatigue properties of passivation layer material with TCT reliability.

TDR measurement of a solder under temperature cycle test

2016 ◽  
Author(s):  
Qihai Li ◽  
Wenxiao Fang ◽  
Jing Xiao ◽  
Weiming Li ◽  
Weiwei Chen ◽  
...  
Keyword(s):  
Temperature Cycle ◽  
Temperature Cycle Test
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