Novel stable sram for ultra low power deep submicron cache memories

Author(s):  
H.P. Rajani ◽  
Hansraj Guhilot ◽  
S.Y. Kulkanri
VLSI Design ◽  
2011 ◽  
Vol 2011 ◽  
pp. 1-19 ◽  
Author(s):  
Subhra Dhar ◽  
Manisha Pattanaik ◽  
Poolla Rajaram

In recent years, the demand for power sensitive designs has grown significantly due to the fast growth of battery-operated portable applications. As the technology scaling continues unabated, subthreshold device design has gained a lot of attention due to the low-power and ultra-low-power consumption in various applications. Design of low-power high-performance submicron and deep submicron CMOS devices and circuits is a big challenge. Short-channel effect is a major challenge for scaling the gate length down and below 0.1 μm. Detailed review and potential solutions for prolonging CMOS as the leading information technology proposed by various researchers in the past two decades are presented in this paper. This paper attempts to categorize the challenges and solutions for low-power and low-voltage application and thus provides a roadmap for device designers working in the submicron and deep submicron region of CMOS devices separately.


2016 ◽  
Vol 136 (11) ◽  
pp. 1555-1566 ◽  
Author(s):  
Jun Fujiwara ◽  
Hiroshi Harada ◽  
Takuya Kawata ◽  
Kentaro Sakamoto ◽  
Sota Tsuchiya ◽  
...  

2010 ◽  
Vol E93-C (6) ◽  
pp. 785-795
Author(s):  
Sung-Jin KIM ◽  
Minchang CHO ◽  
SeongHwan CHO
Keyword(s):  
Rfid Tag ◽  

Nano Letters ◽  
2013 ◽  
Vol 13 (4) ◽  
pp. 1451-1456 ◽  
Author(s):  
T. Barois ◽  
A. Ayari ◽  
P. Vincent ◽  
S. Perisanu ◽  
P. Poncharal ◽  
...  

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