On the definition of real conditions for a fault injection experiment on embedded systems

2011 ◽  
Author(s):  
Felipe Restrepo-Calle ◽  
Sergio Cuenca-Asensi ◽  
Miguel A. Aguirre ◽  
Francisco R. Palomo ◽  
Hipolito Guzman-Miranda ◽  
...  
Keyword(s):  
Embedded Systems ◽  
Fault Injection ◽  
Definition Of ◽  
Injection Experiment

scholarly journals Fluid induced seismicity guided by a continental fault: Injection experiment of 2004/2005 at the German Deep Drilling Site (KTB)

2006 ◽  
Vol 33 (1) ◽  
pp. n/a-n/a ◽  
Author(s):  
S. A. Shapiro ◽  
J. Kummerow ◽  
C. Dinske ◽  
G. Asch ◽  
E. Rothert ◽  
...  
Keyword(s):  
Induced Seismicity ◽  
Fault Injection ◽  
Deep Drilling ◽  
Drilling Site ◽  
Injection Experiment

UML as Front-End Language for Embedded Systems Design

2010 ◽  
pp. 1-23
Author(s):  
Lisane Brisolara de Brisolara ◽  
Marcio Eduardo Kreutz ◽  
Luigi Carro
Keyword(s):  
Embedded Systems ◽  
Embedded System ◽  
Systems Design ◽  
Design Flow ◽  
Domain Specific ◽  
History Of ◽  
Uml Diagrams ◽  
The Embedded System ◽  
Definition Of

This chapter covers the use of UML as a modeling language for embedded systems design. It introduces the UML language, presenting the history of its definition, its main diagrams and characteristics. Using a case study, we show that using the standard UML with its limitations one is not able to model many important characteristics of embedded systems. For that reason, UML provides extension mechanisms that enable one to extend the language for a given domain, through the definition of profiles covering domain-specific applications. Several profiles have been proposed for the embedded systems domain, and some of those that have been standardized by OMG are presented here. A case study is also used to present MARTE, a new profile specifically proposed for the embedded system domain, enabling designers to model aspects like performance and schedulability. This chapter also presents a discussion about the effort to generate code from UML diagrams and analyses the open issues to the successful use of UML in the whole embedded system design flow.

Fault-injection based backdoors in Pseudo Random Number Generators

2015 ◽  
Vol 52 (2) ◽  
pp. 233-245 ◽  
Author(s):  
Norbert Tihanyi
Keyword(s):  
Embedded Systems ◽  
Random Number ◽  
Fault Injection ◽  
Hardware Security ◽  
Smart Cards ◽  
Random Number Generators ◽  
Pseudo Random Number ◽  
Injection Techniques ◽  
Hardware Security Modules

The main aim of this paper is to present the concept of fault-injection backdoors in Random Number Generators. Backdoors can be activated by fault-injection techniques. Presented algorithms can be used in embedded systems like smart-cards and hardware security modules in order to implement subliminal channels in random number generators.

scholarly journals Analysis of the Critical Bits of a RISC-V Processor Implemented in an SRAM-Based FPGA for Space Applications

Electronics ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 175 ◽  
Author(s):  
Luis Alberto Aranda ◽  
Nils-Johan Wessman ◽  
Lucana Santos ◽  
Alfonso Sánchez-Macián ◽  
Jan Andersson ◽  
...  
Keyword(s):  
Ad Hoc ◽  
Fault Tolerant ◽  
Fault Injection ◽  
Electronic Components ◽  
Fpga Design ◽  
Specific Nature ◽  
Space Applications ◽  
Onboard Computer ◽  
Target Architecture ◽  
Definition Of

One of the traditional issues in space missions is the reliability of the electronic components on board spacecraft. There are numerous techniques to deal with this, from shielding and rad-hard fabrication to ad-hoc fault-tolerant designs. Although many of these solutions have been extensively studied, the recent utilization of FPGAs as the target architecture for many electronic components has opened new possibilities, partly due to the distinct nature of these devices. In this study, we performed fault injection experiments to determine if a RISC-V soft processor implemented in an FPGA could be used as an onboard computer for space applications, and how the specific nature of FPGAs needs to be tackled differently from how ASICs have been traditionally handled. In particular, in this paper, the classic definition of the cross-section is revisited, putting into perspective the importance of the so-called “critical bits” in an FPGA design.

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