A Novel Generation Algorithm of Pair-Wise Testing Cases

2009 ◽  
Author(s):  
Jianhua Gao ◽  
Yuefeng Hu
Keyword(s):  
Generation Algorithm

Reduction of Pixel Occurrences in Background Updating

2012 ◽  
Vol 17 (4) ◽  
pp. 45-50
Author(s):  
Zbigniew Bubliński ◽  
Piotr Pawlik
Keyword(s):  
Moving Objects ◽  
Time Rate ◽  
Generation Algorithm ◽  
Modified Method ◽  
Background Updating

Abstract The paper presents the modification of background generation algorithm based on analysis of the frequency of occurrences of pixels. The proposed solution allows the generation of the background and its updating, the introduced parameter allows to adjust the algorithm according to the time rate of changes in the image. The results show that the modified method can be applied in many tasks related to the detection and analysis of moving objects.

BCL::Conf – Improved Open-Source Knowledge-Based Conformation Sampling using the Crystallographic Open Database

2020 ◽  
Author(s):  
Jeffrey Mendenhall ◽  
Benjamin Brown ◽  
Sandeepkumar Kothiwale ◽  
Jens Meiler
Keyword(s):  
Ligand Binding ◽  
Open Source ◽  
Operating Systems ◽  
Generation Algorithm ◽  
Rotamer Library ◽  
Conformer Generation ◽  
Knowledge Based

<div>This paper describes recent improvements made to the BCL::Conf rotamer generation algorithm and comparison of its performance against other freely available and commercial conformer generation software. We demonstrate that BCL::Conf, with the use of rotamers derived from the COD, more effectively recovers crystallographic ligand-binding conformations seen in the PDB than other commercial and freely available software. BCL::Conf is now distributed with the COD-derived rotamer library, free for academic use. The BCL can be downloaded at <a href="http://meilerlab.org/index.php/bclcommons/show/b_apps_id/1">http://meilerlab.org/ bclcommons</a> for Windows, Linux, or Apple operating systems.<br></div>

Low Power and High Speed Sequential Circuits Test Architecture

2019 ◽  
Vol 12 ◽  
Author(s):  
Ahmed K. Jameil ◽  
Yasir Amer Abbas ◽  
Saad Al-Azawi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Test Generation ◽  
High Speed ◽  
Fir Filter ◽  
Sequential Circuits ◽  
Fir Filters ◽  
Design Verification ◽  
Sequential Circuit ◽  
Generation Algorithm

Background: The designed circuits are tested for faults detection in fabrication to determine which devices are defective. The design verification is performed to ensure that the circuit performs the required functions after manufacturing. Design verification is regarded as a test form in both sequential and combinational circuits. The analysis of sequential circuits test is more difficult than in the combinational circuit test. However, algorithms can be used to test any type of sequential circuit regardless of its composition. An important sequential circuit is the finite impulse response (FIR) filters that are widely used in digital signal processing applications. Objective: This paper presented a new design under test (DUT) algorithm for 4-and 8-tap FIR filters. Also, the FIR filter and the proposed DUT algorithm is implemented using field programmable gate arrays (FPGA). Method: The proposed test generation algorithm is implemented in VHDL using Xilinx ISE V14.5 design suite and verified by simulation. The test generation algorithm used FIR filtering redundant faults to obtain a set of target faults for DUT. The fault simulation is used in DUT to assess the benefit of test pattern in fault coverage. Results: The proposed technique provides average reductions of 20 % and 38.8 % in time delay with 57.39 % and 75 % reductions in power consumption and 28.89 % and 28.89 % slices reductions for 4- and 8-tap FIR filter, respectively compared to similar techniques. Conclusions: The results of implementation proved that a high speed and low power consumption design can be achieved. Further, the speed of the proposed architecture is faster than that of existing techniques.

scholarly journals Formation Control and Obstacle Avoidance Algorithm of a Multi-USV System Based on Virtual Structure and Artificial Potential Field

2021 ◽  
Vol 9 (2) ◽  
pp. 161
Author(s):  
Xun Yan ◽  
Dapeng Jiang ◽  
Runlong Miao ◽  
Yulong Li
Keyword(s):  
Obstacle Avoidance ◽  
Potential Field ◽  
Formation Control ◽  
Shape Change ◽  
Artificial Potential Field ◽  
Generation Algorithm ◽  
Time Performance ◽  
Movement Ability ◽  
Window Approach ◽  
Avoidance Problem

This paper proposes a formation generation algorithm and formation obstacle avoidance strategy for multiple unmanned surface vehicles (USVs). The proposed formation generation algorithm implements an approach combining a virtual structure and artificial potential field (VSAPF), which provides a high accuracy of formation shape keeping and flexibility of formation shape change. To solve the obstacle avoidance problem of the multi-USV system, an improved dynamic window approach is applied to the formation reference point, which considers the movement ability of the USV. By applying this method, the USV formation can avoid obstacles while maintaining its shape. The combination of the virtual structure and artificial potential field has the advantage of less calculations, so that it can ensure the real-time performance of the algorithm and convenience for deployment on an actual USV. Various simulation results for a group of USVs are provided to demonstrate the effectiveness of the proposed algorithms.

scholarly journals A column-and-constraint generation algorithm for two-stage stochastic programming problems

Top ◽  
2021 ◽  
Author(s):  
Denise D. Tönissen ◽  
Joachim J. Arts ◽  
Zuo-Jun Max Shen
Keyword(s):  
Stochastic Programming ◽  
Benders Decomposition ◽  
Equivalent Model ◽  
Computational Time ◽  
Two Stage ◽  
Generation Algorithm ◽  
Constraint Generation ◽  
Deterministic Equivalent ◽  
Location Routing ◽  
Relative Tolerance

AbstractThis paper presents a column-and-constraint generation algorithm for two-stage stochastic programming problems. A distinctive feature of the algorithm is that it does not assume fixed recourse and as a consequence the values and dimensions of the recourse matrix can be uncertain. The proposed algorithm contains multi-cut (partial) Benders decomposition and the deterministic equivalent model as special cases and can be used to trade-off computational speed and memory requirements. The algorithm outperforms multi-cut (partial) Benders decomposition in computational time and the deterministic equivalent model in memory requirements for a maintenance location routing problem. In addition, for instances with a large number of scenarios, the algorithm outperforms the deterministic equivalent model in both computational time and memory requirements. Furthermore, we present an adaptive relative tolerance for instances for which the solution time of the master problem is the bottleneck and the slave problems can be solved relatively efficiently. The adaptive relative tolerance is large in early iterations and converges to zero for the final iteration(s) of the algorithm. The combination of this relative adaptive tolerance with the proposed algorithm decreases the computational time of our instances even further.

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