scholarly journals Principles of multi-level reflection for fault tolerant architectures

2003 ◽  
Author(s):  
F. Taiani ◽  
J.-C. Fabre ◽  
M.-O. Killijian
Keyword(s):  
Fault Tolerant ◽  
Multi Level

scholarly journals Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays

2007 ◽  
Author(s):  
M. Haykel Ben Jamaa ◽  
David Atienza ◽  
Giovanni De Micheli ◽  
Kirsten E. Moselund ◽  
Didier Bouvet ◽  
...  
Keyword(s):  
Fault Tolerant ◽  
Multi Level ◽  
Memory Arrays

scholarly journals Fault-Tolerant Operation Strategy for Reliability improvement of a Switched-Capacitor Multi-Level Inverter

2021 ◽  
pp. 1-1
Author(s):  
Mohammadjavad Hassani ◽  
Erfan Azimi ◽  
Aryorad Khodaparast ◽  
Jafar Adabi ◽  
Edris Pouresmaeil
Keyword(s):  
Fault Tolerant ◽  
Switched Capacitor ◽  
Operation Strategy ◽  
Reliability Improvement ◽  
Multi Level

DESIGN OF A MULTI-LEVEL FAULT-TOLERANT MESH (MFTM) FOR HIGH RELIABILITY APPLICATIONS

1995 ◽  
Vol 02 (04) ◽  
pp. 419-429
Author(s):  
SHAMBHU J. UPADHYAYA ◽  
I-SHYAN HWANG
Keyword(s):  
System Reliability ◽  
Fault Tolerant ◽  
High Reliability ◽  
Operational Reliability ◽  
Variable Number ◽  
Hierarchical Design ◽  
Processor Arrays ◽  
Design Paradigm ◽  
Multi Level ◽  
Overall Reliability

This paper presents a novel technique for the enhancement of operational reliability of processor arrays by a multi-level fault-tolerant design approach. The key idea of the design is based on the well known hierarchical design paradigm. The proposed fault-tolerant architecture uses a flexible reconfiguration of redundant nodes, thereby offering a better spare utilization than existing two-level redundancy schemes. A variable number of spares is provided at each level of redundancy which enables a flexible reconfiguration as well as area efficient layouts and better spare utilization. The spare nodes at each level can replace any of the failed primary nodes, not only at the same level but also those at the lower levels. The architecture can be adopted to increase the system reliability in Multi Chip Modules (MCMs). The main contributions of our work are the higher degree of fault tolerance, higher overall reliability, flexibility, and a better spare utilization.

scholarly journals An Integrated Approach to the Design of Fault Tolerant Computing Systems

1974 ◽  
Vol 3 (32) ◽  
Author(s):  
L. Phillip Caillouet ◽  
Bruce D. Shriver
Keyword(s):  
Computer Architecture ◽  
Virtual Machines ◽  
Fault Tolerant ◽  
Research Effort ◽  
Integrated Approach ◽  
Computing System ◽  
Minimal Set ◽  
Computing Systems ◽  
Multi Level ◽  
The University

This paper offers an introduction to a research effort in fault tolerant computer architecture which has been organized at the University of Southwestern Louisiana (USL). It is intended as an overview of several topics which have been isolated for study, and as an indication of preliminary undertakings with regards to one particular topic. This first area of concentration lnvolves the systematic design of fault tolerant computing systems via a multi-level approach. Efforts are being initiated also in the areas of diagnosis of microprogrammable processors via firmware, fault data management across levels of virtual machines, development of a methodology for realizing a firmware hardcore on a variety of hosts, and delineation of a minimal set of resources for the design of a practical host for a multi-level fault tolerant computing system. The research is being conducted under the auspices of Project Beta at USL.

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