Evaluating low-cost fault-tolerance mechanism for microprocessors on multimedia applications

2002 ◽  
Author(s):  
T. Sato ◽  
I. Arita
Keyword(s):  
Fault Tolerance ◽  
Low Cost ◽  
Multimedia Applications ◽  
Tolerance Mechanism

scholarly journals Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2074
Author(s):  
J.-Carlos Baraza-Calvo ◽  
Joaquín Gracia-Morán ◽  
Luis-J. Saiz-Adalid ◽  
Daniel Gil-Tomás ◽  
Pedro-J. Gil-Vicente
Keyword(s):  
Fault Tolerance ◽  
Error Correction ◽  
Error Detection ◽  
Fault Injection ◽  
Error Correction Codes ◽  
Transient Faults ◽  
Tolerance Mechanism ◽  
Intermittent Faults ◽  
Risc Processor ◽  
Simulation Based

Due to transistor shrinking, intermittent faults are a major concern in current digital systems. This work presents an adaptive fault tolerance mechanism based on error correction codes (ECC), able to modify its behavior when the error conditions change without increasing the redundancy. As a case example, we have designed a mechanism that can detect intermittent faults and swap from an initial generic ECC to a specific ECC capable of tolerating one intermittent fault. We have inserted the mechanism in the memory system of a 32-bit RISC processor and validated it by using VHDL simulation-based fault injection. We have used two (39, 32) codes: a single error correction–double error detection (SEC–DED) and a code developed by our research group, called EPB3932, capable of correcting single errors and double and triple adjacent errors that include a bit previously tagged as error-prone. The results of injecting transient, intermittent, and combinations of intermittent and transient faults show that the proposed mechanism works properly. As an example, the percentage of failures and latent errors is 0% when injecting a triple adjacent fault after an intermittent stuck-at fault. We have synthesized the adaptive fault tolerance mechanism proposed in two types of FPGAs: non-reconfigurable and partially reconfigurable. In both cases, the overhead introduced is affordable in terms of hardware, time and power consumption.

Provisioning of Multimedia Applications across Heterogeneous All-IP Networks

2007 ◽  
pp. 796-803 ◽  
Author(s):  
M. Tsagkaropoulos ◽  
I. Politis ◽  
T. Dagiuklas
Keyword(s):  
Credit Card ◽  
Business Models ◽  
Service Providers ◽  
Low Cost ◽  
Multimedia Applications ◽  
Shopping Mall ◽  
Coffee Shop ◽  
Access Technology ◽  
Generation Network ◽  
Multiple Services

With the opening of the telecommunication market and the emergence of low-cost and heterogeneous wireless access technologies, it is envisaged that next-generation network and service providers will not only vary in the deployed access technology but also in their business models and structures. Such providers will differ from large providers such as the current telecom providers offering multiple services and covering large geographical areas, down to small providers offering certain services such as conferencing or messaging only or covering small geographical areas such as a coffee shop or a shopping mall. Further, while in the current networking environment, a home provider of a user is usually represented by a large telecom provider; in such a heterogeneous environment, any trustworthy entity such as an application provider, a banking entity, or a credit card provider that is capable of authenticating the user and marinating his usage profile can act as a home provider. Towards this vision this article discusses the issues that concern the establishment of multimedia applications across heterogeneous networks.

Low-cost fault tolerance in evolvable multiprocessor systems: a graceful degradation approach

2009 ◽  
Vol 10 (6) ◽  
pp. 922-926 ◽  
Author(s):  
Shervin Vakili ◽  
Sied Mehdi Fakhraie ◽  
Siamak Mohammadi ◽  
Ali Ahmadi
Keyword(s):  
Fault Tolerance ◽  
Low Cost ◽  
Multiprocessor Systems ◽  
Graceful Degradation
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