A rule-based tabu search technique for power system decomposition

Author(s):  
M. Mori ◽  
O. Matsuzaki
Author(s):  
Mohamad Khairuzzaman Mohamad Zamani ◽  
Ismail Musirin ◽  
Saiful Izwan Suliman ◽  
Tarek Bouktir

<p>Due to the ever-increasing energy demand, power system operators have attempted to cope with these demands while keeping the power system remain operable. Economic constraints have forced the power system operator to abandon their effort in expanding the power system. The increased load demand can cause the power system to suffer from voltage instability and voltage collapse, especially during contingency condition. Hence, a strategy is required to maintain the steady state operation of a power system. Various research has been conducted to tackle this problem. Therefore, this paper presents the implementation of Chaos Embedded Symbiotic Organisms Search technique to solve optimal FACTS device allocation problem in power transmission system. Various practical constraints are also considered in the optimisation process to emulate the real-life constraints in power system. The optimisation process is conducted on a 26-bus IEEE RTS has validated that the results obtained has not violated the power system stability. The results provided by the proposed optimisation technique has successfully improved the voltage profile and voltage security in the system. Comparative studies are also conducted involving Particle Swarm Optimization and Evolutionary Programming technique resulting good results agreement and superiority of the proposed technique. Results obtained from this study would be beneficial to the power system operators regarding optimisation in power system operation for the implementation in real power transmission network.</p>


Energies ◽  
2015 ◽  
Vol 8 (10) ◽  
pp. 11315-11341 ◽  
Author(s):  
Fei Tang ◽  
Huizhi Zhou ◽  
Qinghua Wu ◽  
Hu Qin ◽  
Jun Jia ◽  
...  

VLSI Design ◽  
2001 ◽  
Vol 12 (1) ◽  
pp. 13-23
Author(s):  
John M. Emmert ◽  
Dinesh K. Bhatia

Search based placement of modules is an important problem in VLSI design. It is always desired that the search should converge quickly to a high quality solution. This paper presents a tabu search based optimization technique to place modules on a regular two-dimensional array. The goal of the technique is to speed up the placement process. The technique is based on a two-step placement strategy. The first step is targeted toward improving circuit routability and the second step addresses circuit performance. The technique is demonstrated through placement of several benchmark circuits on academic as well as commercial FPGAs. Results are compared to placements generated by commercial CAE tools and published simulated annealing based techniques. The tabu search technique compares favorably to published simulated annealing based techniques, and it demonstrates an average execution time speedup of 20 with no impact on quality of results when compared to commercial tools.


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