scholarly journals Design and Evaluation of a High Throughput QoS-Aware and Congestion-Aware Router Architecture for Network-on-Chip

2012 ◽  
Author(s):  
Chifeng Wang ◽  
Nader Bagherzadeh
Keyword(s):  
High Throughput ◽  
Network On Chip ◽  
Router Architecture ◽  
On Chip ◽  
Congestion Aware

scholarly journals Scalable load balancing congestion-aware Network-on-Chip router architecture

2013 ◽  
Vol 79 (4) ◽  
pp. 421-439 ◽  
Author(s):  
Chifeng Wang ◽  
Wen-Hsiang Hu ◽  
Nader Bagherzadeh
Keyword(s):  
Load Balancing ◽  
Network On Chip ◽  
Router Architecture ◽  
On Chip ◽  
Congestion Aware

Pre-allocated Path Based Low Latency Router Architecture for Network-on-chip

2014 ◽  
Vol 35 (2) ◽  
pp. 341-346
Author(s):  
Xiao-fu Zheng ◽  
Hua-xi Gu ◽  
Yin-tang Yang ◽  
Zhong-fan Huang
Keyword(s):  
Network On Chip ◽  
Low Latency ◽  
Router Architecture ◽  
On Chip
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