Performance Models for Matrix Computations on Multicore Processors Using OpenMP

2010 International Conference on Parallel and Distributed Computing, Applications and Technologies ◽

10.1109/pdcat.2010.52 ◽

2010 ◽

Cited By ~ 2

Author(s):

Panagiotis D. Michailidis ◽

Konstantinos G. Margaritis

Keyword(s):

Multicore Processors ◽

Performance Models ◽

Matrix Computations

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LEVERAGING SHARED CACHES FOR PARALLEL TEMPORAL BLOCKING OF STENCIL CODES ON MULTICORE PROCESSORS AND CLUSTERS

Parallel Processing Letters ◽

10.1142/s0129626410000296 ◽

2010 ◽

Vol 20 (04) ◽

pp. 359-376 ◽

Cited By ~ 15

Author(s):

MARKUS WITTMANN ◽

GEORG HAGER ◽

JAN TREIBIG ◽

GERHARD WELLEIN

Keyword(s):

High Speed ◽

Distributed Memory ◽

Multicore Processors ◽

Memory Bandwidth ◽

Performance Models ◽

Shared Caches ◽

Strong Scaling ◽

Stencil Codes ◽

Multicore Chips ◽

Synthetic Modeling

Bandwidth-starved multicore chips have become ubiquitous. It is well known that the performance of stencil codes can be improved by temporal blocking, lessening the pressure on the memory interface. We introduce a new pipelined approach that makes explicit use of shared caches in multicore environments and minimizes synchronization and boundary overhead. Benchmark results are presented for three current x86-based microprocessors, showing clearly that our optimization works best on designs with high-speed shared caches and low memory bandwidth per core. We furthermore demonstrate that simple bandwidth-based performance models are inaccurate for this kind of algorithm and employ a more elaborate, synthetic modeling procedure. Finally we show that temporal blocking can be employed successfully in a hybrid shared/distributed-memory environment, albeit with limited benefit at strong scaling.

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