The long way to power efficient, high performance DRAMs

2016 ◽  
Author(s):  
Klaus Hofmann ◽  
Tu Darmstadt
Keyword(s):  
High Performance ◽  
Power Efficient

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

scholarly journals Environmental Sound Recognition on Embedded Systems: From FPGAs to TPUs

Electronics ◽  
2021 ◽  
Vol 10 (21) ◽  
pp. 2622
Author(s):  
Jurgen Vandendriessche ◽  
Nick Wouters ◽  
Bruno da Silva ◽  
Mimoun Lamrini ◽  
Mohamed Yassin Chkouri ◽  
...  
Keyword(s):  
Machine Learning ◽  
High Performance ◽  
Machine Learning Techniques ◽  
Sound Recognition ◽  
Learning Approaches ◽  
Environmental Sound ◽  
Embedded Devices ◽  
Power Efficient ◽  
Computationally Intensive ◽  
Environmental Sound Recognition

In recent years, Environmental Sound Recognition (ESR) has become a relevant capability for urban monitoring applications. The techniques for automated sound recognition often rely on machine learning approaches, which have increased in complexity in order to achieve higher accuracy. Nonetheless, such machine learning techniques often have to be deployed on resource and power-constrained embedded devices, which has become a challenge with the adoption of deep learning approaches based on Convolutional Neural Networks (CNNs). Field-Programmable Gate Arrays (FPGAs) are power efficient and highly suitable for computationally intensive algorithms like CNNs. By fully exploiting their parallel nature, they have the potential to accelerate the inference time as compared to other embedded devices. Similarly, dedicated architectures to accelerate Artificial Intelligence (AI) such as Tensor Processing Units (TPUs) promise to deliver high accuracy while achieving high performance. In this work, we evaluate existing tool flows to deploy CNN models on FPGAs as well as on TPU platforms. We propose and adjust several CNN-based sound classifiers to be embedded on such hardware accelerators. The results demonstrate the maturity of the existing tools and how FPGAs can be exploited to outperform TPUs.

Power-efficient and high-performance block I/O framework for mobile virtualization systems

2016 ◽  
Vol 73 (4) ◽  
pp. 1307-1321 ◽  
Author(s):  
Kihong Lee ◽  
DongWoo Lee ◽  
Sungkil Lee ◽  
Young Ik Eom
Keyword(s):  
High Performance ◽  
Power Efficient

Analyzing the Robustness of HPC Applications Using a Fine-Grained Soft Error Fault Injection Tool

2016 ◽  
pp. 277-305
Author(s):  
Qiang Guan ◽  
Nathan DeBardeleben ◽  
Sean Blanchard ◽  
Song Fu ◽  
Claude H. Davis IV ◽  
...  
Keyword(s):  
High Performance ◽  
Fault Injection ◽  
Soft Errors ◽  
Small Degree ◽  
Soft Error ◽  
Power Efficient ◽  
Fine Grained ◽  
Different Characteristics ◽  
The Impact ◽  
Performance Computing

As the high performance computing (HPC) community continues to push towards exascale computing, HPC applications of today are only affected by soft errors to a small degree but we expect that this will become a more serious issue as HPC systems grow. We propose F-SEFI, a Fine-grained Soft Error Fault Injector, as a tool for profiling software robustness against soft errors. We utilize soft error injection to mimic the impact of errors on logic circuit behavior. Leveraging the open source virtual machine hypervisor QEMU, F-SEFI enables users to modify emulated machine instructions to introduce soft errors. F-SEFI can control what application, which sub-function, when and how to inject soft errors with different granularities, without interference to other applications that share the same environment. We demonstrate use cases of F-SEFI on several benchmark applications with different characteristics to show how data corruption can propagate to incorrect results. The findings from the fault injection campaign can be used for designing robust software and power-efficient hardware.

LOW POWER AND HIGH PERFORMANCE SINGLE-ENDED SENSE AMPLIFIER

2013 ◽  
Vol 22 (07) ◽  
pp. 1350062 ◽  
Author(s):  
AJAY KUMAR SINGH ◽  
MAH MENG SEONG ◽  
C. M. R. PRABHU
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Voltage Drop ◽  
Cmos Technology ◽  
Power Efficient ◽  
Sense Amplifier ◽  
Current Voltage ◽  
Direct Current Voltage ◽  
Voltage Conversion ◽  
Lower Voltage

This paper presents a new power efficient single ended sense amplifier (SA). The proposed circuit is based on the direct current voltage conversion technique. It has been simulated using Microwind3 and DSCH3 tools (advanced BSIM 4 level) for 90 nm CMOS technology in terms of power consumption, sense time and results were compared to other circuits. The proposed SA circuit consumes more than 50% less power and gives 90% faster sensing speed compared to other circuits. The lower power consumption is due to lower leakage current, lower voltage drop on bit-line and faster speed is due to positive feedback of the circuit. The proposed circuit is more robust against any process and temperature variation.

Chip Level Refrigeration of Portable Electronic Equipment Using Thermoelectric Devices

2003 ◽  
Author(s):  
Gary L. Solbrekken ◽  
Kazuaki Yazawa ◽  
Avram Bar-Cohen
Keyword(s):  
Thermal Resistance ◽  
Heat Sink ◽  
High Performance ◽  
Heat Dissipation ◽  
Electronic Equipment ◽  
Interfacial Thermal Resistance ◽  
Maximum Heat ◽  
Power Efficient ◽  
System Sensitivity ◽  
Heat Pumping

It is well established that the power dissipation for electronic components is increasing. At the same time, high performance portable equipment with volume, weight, and power limitations are gaining widespread acceptance in the marketplace. The combination of the above conditions requires thermal solutions that are high performance and yet small, light, and power efficient. This paper explores the possibility of using thermoelectric (TE) refrigeration as an integrated solution for portable electronic equipment accounting for heat sink and interface material thermal resistances. The current study shows that TE refrigeration can indeed have a benefit over using just a heat sink. Performance maps illustrating where TE refrigeration offers an advantage over an air-cooled heat sink are created for a parametric range of CPU heat flows, heat sink thermal resistances, and TE material properties. During the course of the study, it was found that setting the TE operating current based on minimizing the CPU temperature (Tj), as opposed to maximizing the amount of heat pumping, significantly reduces Tj. For the baseline case studied, a reduction of 20–30°C was demonstrated over a range of CPU heat dissipation. The parametric studies also illustrate that management of the heat sink thermal resistance appears to be more critical than the CPU/TE interfacial thermal resistance. However, setting the TE current based on a minimum Tj as opposed to maximum heat pumping reduces the system sensitivity to the heat sink thermal resistance.

Sign in / Sign up

Export Citation Format

Share Document