Compact multi-function single/dual-beam graphene lens antenna for terahertz applications

2016 ◽  
Author(s):  
W. M. Hassan ◽  
S. H. Zainud-Deen ◽  
H. A. Malhat
Keyword(s):  
Lens Antenna ◽  
Dual Beam ◽  
Terahertz Applications

High-Gain Circularly Polarized Lens Antenna for Terahertz Applications

2019 ◽  
Vol 18 (5) ◽  
pp. 921-925 ◽  
Author(s):  
Geng Bo Wu ◽  
Yuan-Song Zeng ◽  
Ka Fai Chan ◽  
Shi-Wei Qu ◽  
Chi Hou Chan
Keyword(s):  
High Gain ◽  
Lens Antenna ◽  
Circularly Polarized ◽  
Terahertz Applications

scholarly journals Bi-Function Multi-Beam Graphene Lens Antenna for Terahertz Applications

2016 ◽  
Vol 07 (01) ◽  
pp. 36-45 ◽  
Author(s):  
Saber H. Zainud-Deen ◽  
Walaa M. Hassan ◽  
Hend A. Malhat
Keyword(s):  
Lens Antenna ◽  
Terahertz Applications

3D Investigations of Plasma Erosion Craters using FIB/SEM Dual-Beam Techniques

2006 ◽  
Vol 43 (9) ◽  
pp. 470-482 ◽  
Author(s):  
Nicolas Jeanvoine ◽  
Christian Holzapfel ◽  
Flavio Soldera ◽  
Frank Mücklich
Keyword(s):  
Dual Beam ◽  
Plasma Erosion

Application of Automated FIB for TEM Sample Preparation in Semiconductor Failure Analysis

2014 ◽  
Author(s):  
Jie Zhu ◽  
Soo Sien Seah ◽  
Irene Tee ◽  
Bing Hai Liu ◽  
Eddie Er ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Success Rate ◽  
Protective Layer ◽  
Factors Affecting ◽  
Dual Beam ◽  
Lamella Thickness ◽  
Surface Patterns ◽  
Working Parameters ◽  
Practical Factors ◽  
High Flexibility

Abstract In this paper, we describe automated FIB for TEM sample preparation using iFast software on a Helios 450HP dual-beam system. A robust iFast automation recipe needs to consider as many variables as possible in order to ensure consistent sample quality and high success rate. Variations mainly come from samples of different materials, structures, surface patterns, surface topography and surface charging. The recipe also needs to be user-friendly and provide high flexibility by allowing users to choose preferable working parameters for specific types of samples, such as: grounding, protective layer coating, milling steps, and final TEM lamella thickness/width. In addition to the iFast recipe, other practical factors affecting automation success rate are also discussed and highlighted.

To Eliminate Curtain Effect of FIB TEM Samples by a Combination of Sample Dicing and Backside Milling

2014 ◽  
Author(s):  
Jian-Shing Luo ◽  
Hsiu Ting Lee
Keyword(s):  
Sample Preparation ◽  
Focused Ion Beam ◽  
Preparation Method ◽  
Low Cost ◽  
Ion Beam ◽  
Sample Preparation Method ◽  
Site Specific ◽  
Dual Beam ◽  
Transmission Electron

Abstract Several methods are used to invert samples 180 deg in a dual beam focused ion beam (FIB) system for backside milling by a specific in-situ lift out system or stages. However, most of those methods occupied too much time on FIB systems or requires a specific in-situ lift out system. This paper provides a novel transmission electron microscopy (TEM) sample preparation method to eliminate the curtain effect completely by a combination of backside milling and sample dicing with low cost and less FIB time. The procedures of the TEM pre-thinned sample preparation method using a combination of sample dicing and backside milling are described step by step. From the analysis results, the method has applied successfully to eliminate the curtain effect of dual beam FIB TEM samples for both random and site specific addresses.

The Novel TEM Sample Preparation Approach for Targeted via with Barrier/Cu Seed Layer Inspection

2009 ◽  
Author(s):  
Wen-Fei Hsieh ◽  
Shih-Hsiang Tseng ◽  
Bo Min She
Keyword(s):  
Sample Preparation ◽  
Cross Section ◽  
Seed Layer ◽  
Target Location ◽  
Process Development ◽  
Process Integration ◽  
Ion Beam ◽  
Main Tool ◽  
Dual Beam ◽  
Sample Preparation Procedure

Abstract In this study, an FIB-based cross section TEM sample preparation procedure for targeted via with barrier/Cu seed layer is introduced. The dual beam FIB with electron beam for target location and Ga ion beam for sample milling is the main tool for the targeted via with barrier/Cu seed layer inspection. With the help of the FIB operation and epoxy layer protection, ta cross section TEM sample at a targeted via with barrier/Cu seed layer could be made. Subsequent TEM inspection is used to verify the quality of the structure. This approach was used in the Cu process integration performance monitor. All these TEM results are very helpful in process development and yield improvement.

Manufacturing In-Line Whole Wafer Focused Ion Beam (FIB) Memory Address Descramble Verification

2008 ◽  
Author(s):  
Steven B. Herschbein ◽  
Hyoung H. Kang ◽  
Scott L. Jansen ◽  
Andrew S. Dalton
Keyword(s):  
Flip Chip ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Random Access ◽  
Cell Counting ◽  
Test Results ◽  
Laboratory Procedure ◽  
Memory Array ◽  
Dual Beam ◽  
Process Level

Abstract Test engineers and failure analyst familiar with random access memory arrays have probably encountered the frustration of dealing with address descrambling. The resulting nonsequential internal bit cell counting scheme often means that the location of the failing cell under investigation is nowhere near where it is expected to be. A logical to physical algorithm for decoding the standard library block might have been provided with the design, but is it still correct now that the array has been halved and inverted to fit the available space in a new processor chip? Off-line labs have traditionally been tasked with array layout verification. In the past, hard and soft failures could be induced on the frontside of finished product, then bitmapped to see if the sites were in agreement. As density tightened, flip-chip FIB techniques to induce a pattern of hard fails on packaged devices came into practice. While the backside FIB edit method is effective, it is complex and expensive. The installation of an in-line Dual Beam FIB created new opportunities to move FA tasks out of the lab and into the FAB. Using a new edit procedure, selected wafers have an extensive pattern of defects 'written' directly into the memory array at an early process level. Bitmapping of the RAM blocks upon wafer completion is then used to verify correlation between the physical damaged cells and the logical sites called out in the test results. This early feedback in-line methodology has worked so well that it has almost entirely displaced the complex laboratory procedure of backside FIB memory array descramble verification.

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