Flexible network address mapping for container-based clouds

2015 ◽  
Author(s):  
Kyung-Hwa Kim ◽  
Jae Woo Lee ◽  
Michael Ben-Ami ◽  
Hyunwoo Nam ◽  
Jan Janak ◽  
...  
Keyword(s):  
Address Mapping

Static Analysis of Run-Time Inter-Core Interferences for Concurrent Programs in Shared Cache Multicore Architectures

2012 ◽  
Vol 198-199 ◽  
pp. 523-527
Author(s):  
Fang Yuan Chen ◽  
Dong Song Zhang ◽  
Zhi Ying Wang
Keyword(s):  
Multicore Processors ◽  
Mapping Method ◽  
Concurrent Programs ◽  
Multicore Architectures ◽  
Shared Resources ◽  
Worst Case ◽  
Shared Cache ◽  
Address Mapping ◽  
Novel Approach ◽  
Time Systems

Worst-Case Execution Time (WCET) is crucial in real-time systems and is very challenging in multicore processors due to the possible runtime inter-thread interferences caused by shared resources. This paper proposes a novel approach to analyze runtime inter-core interferences for consecutive or inconsecutive concurrent programs. Our approach can reasonably estimate runtime inter-core interferences in shared cache by introducing lifetime and instruction fetching timing relations analysis into address mapping method. Compared with the method based on lifetime alone, our proposed approach efficiently improves the tightness of WCET estimation.

scholarly journals An implementation of low latency address-mapping logic for SSD controllers

2019 ◽  
Vol 16 (21) ◽  
pp. 20190521-20190521
Author(s):  
Yuchan Song ◽  
Hyunjoo So ◽  
Yongjae Chun ◽  
Hyun-Seok Kim ◽  
Youpyo Hong
Keyword(s):  
Low Latency ◽  
Address Mapping

scholarly journals A Design of a Lightweight In-Vehicle Edge Gateway for the Self-Diagnosis of an Autonomous Vehicle

2018 ◽  
Vol 8 (9) ◽  
pp. 1594 ◽  
Author(s):  
YiNa Jeong ◽  
SuRak Son ◽  
EunHee Jeong ◽  
ByungKwan Lee
Keyword(s):  
Delay Time ◽  
Autonomous Vehicle ◽  
Cost Effective ◽  
Transmission Error ◽  
Control Area ◽  
Transmission Delay ◽  
The Self ◽  
Area Network ◽  
Address Mapping ◽  
Control Area Network

This paper proposes a Lightweight In-Vehicle Edge Gateway (LI-VEG) for the self-diagnosis of an autonomous vehicle, which supports a rapid and accurate communication between in-vehicle sensors and a self-diagnosis module and between in-vehicle protocols. A paper on the self-diagnosis module has been published previously, thus this paper only covers the LI-VEG, not the self-diagnosis. The LI-VEG consists of an In-Vehicle Sending and Receiving Layer (InV-SRL), an InV-Management Layer (InV-ML) and an InV-Data Translator Layer (InV-DTL). First, the InV-SRL receives the messages from FlexRay, Control Area Network (CAN), Media Oriented Systems Transport (MOST), and Ethernet and transfers the received messages to the InV-ML. Second, the InV-ML manages the message transmission and reception of FlexRay, CAN, MOST, and Ethernet and an Address Mapping Table. Third, the InV-DTL decomposes the message of FlexRay, CAN, MOST, and Ethernet and recomposes the decomposed messages to the frame suitable for a destination protocol. The performance analysis of the LI-VEG shows that the transmission delay time about message translation and transmission is reduced by an average of 10.83% and the transmission delay time caused by traffic overhead is improved by an average of 0.95%. Therefore, the LI-VEG has higher compatibility and is more cost effective because it applies a software gateway to the OBD, compared to a hardware gateway. In addition, it can reduce the transmission error and overhead caused by message decomposition because of a lightweight message header.

FPGA Implementation of NAND Flash Wear-Levelling Algorithm

2012 ◽  
Vol 241-244 ◽  
pp. 1209-1212
Author(s):  
Ju Hong Wen ◽  
Wei Jiang Wang ◽  
Wei Gao ◽  
Xiao Nan Fan
Keyword(s):  
Fpga Implementation ◽  
Nand Flash ◽  
Reading And Writing ◽  
Address Mapping ◽  
And Storage ◽  
Physical Address

NAND flash would generate invalid blocks during its manufacturing and using, and the invalid block management is a key point of NAND flash. By studying the structure and storage rules of NAND flash, this paper put forward a wear-levelling algorithm against the invalid blocks of NAND flash based on FPGA. This algorithm use invalid block table and logical-physical address mapping table to manage the invalid blocks and do wear-levelling. The design is implemented by VHDL, and successfully realized the wear-levelling and the reading and writing operations of NAND flash.

Amore Address Mapping with Overlapped Rotating Entries

IEEE Micro ◽  
1987 ◽  
Vol 7 (3) ◽  
pp. 22-34
Author(s):  
G.J. Dekker ◽  
A.j. van de Goor
Keyword(s):  
Address Mapping
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