Multi-level Power Consumption and Computation Models and Energy-Efficient Server Selection Algorithms in a Scalable Cluster

2016 ◽  
Author(s):  
Hiroki Kataoka ◽  
Atsuhiro Sawada ◽  
Dilawaer Duolikun ◽  
Tomoya Enokido ◽  
Makoto Takizawa
Keyword(s):  
Power Consumption ◽  
Energy Efficient ◽  
Server Selection ◽  
Multi Level ◽  
Selection Algorithms

Multi-level power consumption model and energy-aware server selection algorithm

2017 ◽  
Vol 8 (3) ◽  
pp. 201 ◽  
Author(s):  
Hiroki Kataoka ◽  
Shigenari Nakamura ◽  
Dilawaer Duolikun ◽  
Tomoya Enokido ◽  
Makoto Takizawa
Keyword(s):  
Power Consumption ◽  
Selection Algorithm ◽  
Energy Aware ◽  
Server Selection ◽  
Multi Level ◽  
Consumption Model

Multi-level power consumption model and energy-aware server selection algorithm

2017 ◽  
Vol 8 (3) ◽  
pp. 201 ◽  
Author(s):  
Hiroki Kataoka ◽  
Shigenari Nakamura ◽  
Dilawaer Duolikun ◽  
Tomoya Enokido ◽  
Makoto Takizawa
Keyword(s):  
Power Consumption ◽  
Selection Algorithm ◽  
Energy Aware ◽  
Server Selection ◽  
Multi Level ◽  
Consumption Model

Multi-level phase-change memory with ultralow power consumption and resistance drift

2021 ◽  
Author(s):  
Bin Liu ◽  
Kaiqi Li ◽  
Wanliang Liu ◽  
Jian Zhou ◽  
Liangcai Wu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Phase Change ◽  
Phase Change Memory ◽  
Multi Level ◽  
Ultralow Power ◽  
Change Memory

scholarly journals An approach to energy efficient lighting design for economic residential flats

2021 ◽  
Vol 850 (1) ◽  
pp. 012013
Author(s):  
Subhasish Das ◽  
Anubrata Mondal ◽  
Kamalika Ghosh
Keyword(s):  
Power Consumption ◽  
Energy Saving ◽  
Energy Efficient ◽  
Residential Building ◽  
Light Level ◽  
Lighting Design ◽  
Wide Range ◽  
Standard Values ◽  
Lighting Systems

Abstract The lighting design in a residential building now-a-days is not only limited to general lighting but also it is focused to provide quality lighting with the help of wide range of available luminaire with different orientations as well as colours with efficient use of energy, that opens up accurate characteristics of specific areas in any room of the building. The affordable housings in many states are some of the examples of residential building where most of the flats in a typical floor are using conventional lighting systems which are not energy efficient and light level is low compared to standards. This paper is mainly focused to provide a budget friendly as well as energy efficient lighting design with the help of new and energy efficient lamps using DIALux Software, which can be proposed to renovate the existing conventional lighting systems. In this paper effort has been made to reduce the power consumption in all rooms and lux levels has been achieved as per standard values along with good amount of energy saving with the use of newer technologies.

scholarly journals Energy-Efficient Hardware Architectures for the Packet Data Convergence Protocol in LTE-Advanced Mobile Terminals

VLSI Design ◽  
2013 ◽  
Vol 2013 ◽  
pp. 1-15
Author(s):  
Shadi Traboulsi ◽  
Valerio Frascolla ◽  
Nils Pohl ◽  
Josef Hausner ◽  
Attila Bilgic
Keyword(s):  
Power Consumption ◽  
Energy Efficient ◽  
Reference Architecture ◽  
Least Significant Bit ◽  
Mobile Terminals ◽  
Standard Cell Library ◽  
Cell Library ◽  
Lte Advanced ◽  
Packet Data ◽  
Hardware Architectures

In this paper, we present and compare efficient low-power hardware architectures for accelerating the Packet Data Convergence Protocol (PDCP) in LTE and LTE-Advanced mobile terminals. Specifically, our work proposes the design of two cores: a crypto engine for the Evolved Packet System Encryption Algorithm (128-EEA2) that is based on the AES cipher and a coprocessor for the Least Significant Bit (LSB) encoding mechanism of the Robust Header Compression (ROHC) algorithm. With respect to the former, first we propose a reference architecture, which reflects a basic implementation of the algorithm, then we identify area and power bottle-necks in the design and finally we introduce and compare several architectures targeting the most power-consuming operations. With respect to the LSB coprocessor, we propose a novel implementation based on a one-hot encoding, thereby reducing hardware’s logic switching rate. Architectural hardware analysis is performed using Faraday’s 90 nm standard-cell library. The obtained results, when compared against the reference architecture, show that these novel architectures achieve significant improvements, namely, 25% in area and 35% in power consumption for the 128-EEA2 crypto-core, and even more important reductions are seen for the LSB coprocessor, that is, 36% in area and 50% in power consumption.

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