An FPGA-based Random Functional Verification Method for Cache

2013 ◽  
Author(s):  
Li Tiejun ◽  
Zhang Jianmin ◽  
Li Sikun
Keyword(s):  
Functional Verification ◽  
Verification Method

scholarly journals A Specification-Based Semi-Formal Functional Verification Method by a Stage Transition Graph Model

IEEE Access ◽  
2019 ◽  
Vol 7 ◽  
pp. 14947-14958
Author(s):  
Zhao Lv ◽  
Shuming Chen ◽  
Tingrong Zhang ◽  
Yaohua Wang
Keyword(s):  
Graph Model ◽  
Functional Verification ◽  
Transition Graph ◽  
Verification Method ◽  
Stage Transition

VERIFICATION OF DATAFLOW SCHEDULING

2008 ◽  
Vol 18 (06) ◽  
pp. 737-758
Author(s):  
TSUNG-HSI CHIANG ◽  
LAN-RONG DUNG
Keyword(s):  
Formal Verification ◽  
Petri Net ◽  
Register Transfer Level ◽  
Functional Verification ◽  
Model Checker ◽  
Symbolic Model ◽  
Verification Method ◽  
Level Design ◽  
High Level ◽  
Design Scheduling

This paper presents the formal verification method for high-level synthesis (HLS) to detect design errors of dataflow algorithms by using Petri Net (PN) and symbolic-model-verifier (SMV) techniques. Formal verification in high-level design means architecture verification, which is different from functional verification in register transfer level (RTL). Generally, dataflow algorithms need algorithmic transformations to achieve optimal goals and also need design scheduling to allocate processor resources before mapping on a silicon. However, algorithmic transformations and design scheduling are error-prone. In order to detect high-level faults, high-level verification is applied to verify the synthesis results in HLS. Instead of applying Boolean algebra in traditional verification, this paper adopts both Petri Net theory and SMV model checker to verify the correctness of the synthesis results of the high-level dataflow designs. In the proposed hybrid verification method, a high-level design or DUV (design-under-verification) is first transformed into a Petri Net model. Then, Petri Net theory is applied to check the correctness of its algorithmic transformations of HLS, and the SMV model checker is used to verify the correctness of the design scheduling. We presented two approaches to realize the proposed verification method and concluded the best one who outperforms the other in terms of processing speed and resource usage.

External Memory Interface Verification Based on VMM

2014 ◽  
Vol 981 ◽  
pp. 103-106
Author(s):  
Rui Xu ◽  
Zhan Peng Jiang ◽  
Chang Chun Dong ◽  
Xue Bin Lu
Keyword(s):  
Complex Function ◽  
External Memory ◽  
Functional Verification ◽  
Verification Method ◽  
Coverage Control ◽  
Memory Interface ◽  
Verification Methodology

With the growth of the scale of SoC, function verification becomes more and more complicated. Traditional functional verification method is confronted with some challenges. This paper achieves coverage-driven, constrained-randomization and assertion verification methodology based on SystemVerilog and VMM, to build verification platform by taking example of EMI (external memory interface). As result of verification, we can monitor coverage, control the platform, optimize testbench and testcase, finish function coverage 100%. These applications can simplify complex function verification, improve the platform reuse, and meet the needs of chip verification.

A Verification Method of Multi-Threaded Processor Based on Tree-Structure

2011 ◽  
Vol 403-408 ◽  
pp. 1865-1868
Author(s):  
Pei Jun Ma ◽  
Meng Liu ◽  
Kang Li ◽  
Jiang Yi Shi
Keyword(s):  
Tree Structure ◽  
Functional Verification ◽  
Feedback Information ◽  
Verification Method ◽  
Functional Coverage ◽  
Coverage Model ◽  
Speed Up ◽  
Structure Instruction

A method based on tree-structure for verifying a multi-threading processor is described in this paper. In this method, instructions are classified according to tree-structure, instruction stream is generated by hierarchical random and the tree-structure is pruned by feedback information of functional coverage model. Results show that this method can speed up the convergence of the coverage and supply effective functional verification for micro-engine.

Sign in / Sign up

Export Citation Format

Share Document