Test Calculation for Logic and Delay Faults in Digital Circuits

2006 ◽  
Author(s):  
Jozsef Sziray
Keyword(s):  
Digital Circuits ◽  
Delay Faults ◽  
Test Calculation

scholarly journals Test Pattern Generation with Low Power for Delay Faults in Digital Circuits by Evolution Method with Hybrid Strategies

2014 ◽  
Vol 8 (1) ◽  
pp. 77-83
Author(s):  
Pan Zhongliang ◽  
Chen Ling ◽  
Chen Yihui
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Digital Circuits ◽  
Test Pattern ◽  
Average Power ◽  
Pattern Generation ◽  
Test Pattern Generation ◽  
Delay Faults ◽  
High Power Consumption ◽  
Test Vectors

The high power consumption during circuit test process can produce unwanted failures or take effects on circuit reliability, therefore the reduction of both peak power and average power of circuit test is necessary. A test pattern generation approach is presented in this paper for the delay faults in digital circuits, the approach makes use of the evolution method with the hybrid strategies to produce the test vectors with low power consumption. First of all, a pair of vectors that may detect a delay fault is coded as an individual. A lot of individuals constitute the populations. Secondly, the test vectors with low power are produced by the evolution of these populations. Many new individuals are randomly produced and are added into every evolution step, and the mutation mode of individuals is related to other individuals in the current population. A lot of experimental results show that the test vectors with low power for the delay faults in digital circuits can be produced by the approach proposed in this paper, and the approach can get the large reduction of power consumption when compared with random test generation algorithm.

Test Approach Based on Decision Diagrams for Delay Fault Caused by Crosstalk Interferences in Digital Circuits

2010 ◽  
Vol 663-665 ◽  
pp. 559-562
Author(s):  
Zhong Liang Pan ◽  
Ling Chen
Keyword(s):  
Digital Circuits ◽  
Timing Analysis ◽  
Decision Diagrams ◽  
Delay Faults ◽  
Static Timing Analysis ◽  
Technology Scaling ◽  
Static Timing ◽  
Delay Sensitive ◽  
Test Vectors ◽  
Selection Of

The crosstalk is induced between the elements in digital circuits due the increasing switching speeds and the decreasing in technology scaling. The crosstalk is caused by parasitic couplings between adjacent wires that include capacitance and inductance effects. The crosstalk can result in functional failures or timing problems. A test approach for the delay faults caused by crosstalk interferences in digital circuits is presented in this paper, the approach is based on decision diagrams and the selection of delay sensitive path. The static timing analysis is carried out to obtain the delay information about the paths, all aggressor lines are activated in the best possible way. The test vectors are generated by building a decision diagram and searching for the specific paths in the decision diagram. Experimental results show that the test approach proposed in this paper can generate the test vectors for the testable delay faults caused by crosstalk.

UNIFIED TECHNIQUE FOR ON-LINE TESTING OF DIGITAL CIRCUITS: DELAY AND STUCK-AT FAULT MODELS

2008 ◽  
Vol 17 (06) ◽  
pp. 1069-1089 ◽  
Author(s):  
S. BISWAS ◽  
S. MUKHOPADHYAY ◽  
A. PATRA ◽  
D. SARKAR
Keyword(s):  
Cell Count ◽  
Digital Circuits ◽  
Deep Submicron ◽  
Line Detection ◽  
Delay Faults ◽  
Fault Models ◽  
Bridging Faults ◽  
Area Overhead ◽  
Transition Faults ◽  
On Line

This work is concerned with the development of generic, nonintrusive, and flexible algorithms for the design of digital circuits with on-line testing (OLT) capability. Most of the works presented in the literature on OLT have used single stuck at (s - a) fault models. However, in the deep submicron technology, single s - a fault models may not capture more than a fraction of the real defects. To cater to the problem it is now advocated that additional fault models such as bridging faults, transition faults, delay faults, etc., are also used. The proposed technique is one of the first works that facilitates a unified scheme for on-line detection of delay faults and s - a faults with a high value of n for n-Detect tests. The technique can handle generic digital circuits with cell count as high as 15,000 and having the order of 2500 states. Results for the design of on-line detectors for various ISCAS89 benchmark circuits are provided. The results illustrate that with marginal increase in the area overhead, if compared to the ones with single s - a fault coverage only, the proposed scheme also provides coverage for the delay faults.

ALL-OPTICAL DIGITAL CIRCUITS

1988 ◽  
Vol 49 (C2) ◽  
pp. C2-459-C2-462 ◽  
Author(s):  
F. A.P. TOOLEY ◽  
B. S. WHERRETT ◽  
N. C. CRAFT ◽  
M. R. TAGHIZADEH ◽  
J. F. SNOWDON ◽  
...  
Keyword(s):  
Digital Circuits ◽  
All Optical
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