scholarly journals Statistical Static Timing Analysis Considering the Impact of Power Supply Noise in VLSI Circuits

2006 ◽  
Author(s):  
Hyun Sung Kim ◽  
D.M.H. Walker
Keyword(s):  
Power Supply ◽  
Timing Analysis ◽  
Vlsi Circuits ◽  
Power Supply Noise ◽  
Static Timing Analysis ◽  
Static Timing ◽  
Supply Noise ◽  
Statistical Static Timing Analysis ◽  
The Impact

STATISTICAL TIMING ANALYSIS OF THE CLOCK PERIOD IMPROVEMENT THROUGH CLOCK SKEW SCHEDULING

2011 ◽  
Vol 20 (05) ◽  
pp. 881-898 ◽  
Author(s):  
SHANNON M. KURTAS ◽  
BARIS TASKIN
Keyword(s):  
Timing Analysis ◽  
Process Variations ◽  
Clock Signal ◽  
Static Timing Analysis ◽  
Clock Skew ◽  
Clock Period ◽  
Static Timing ◽  
Statistical Static Timing Analysis ◽  
Clock Skew Scheduling ◽  
Zero Skew

Statistical static timing analysis (SSTA) methods, which model process variations statistically as probability distribution function rather than deterministically, have been thoroughly performed on traditional zero clock skew circuits. In the traditional zero clock skew circuits, the synchronizing clock signal is designed to arrive in phase with respect to each register. However, designers will often schedule the clock skew to different registers in order to decrease the minimum clock period of the entire circuit. Clock skew scheduling imparts very different timing constraints that are based, in part, on the topology of the circuit. In this paper, SSTA is applied to nonzero clock skew circuits in order to determine the accuracy improvement relative to their zero skew counterparts, and also to assess how the results of skew scheduling might be impacted with more accurate statistical modeling. For 99.7% timing yield (3σ variation), SSTA is observed to improve the accuracy, and therefore increase the timing margin, of nonzero clock skew circuits by up to 2.5×, and on average by 1.3×, the amount seen by zero skew circuits.

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