Guest Editors' Introduction: Interaction of Many-Core Computer Architecture and Operating Systems

IEEE Micro ◽  
2008 ◽  
Vol 28 (3) ◽  
pp. 2-5 ◽  
Author(s):  
Sangyeun Cho ◽  
Tao Li ◽  
Onur Mutlu
Impact ◽  
2019 ◽  
Vol 2019 (10) ◽  
pp. 44-46
Author(s):  
Masato Edahiro ◽  
Masaki Gondo

The pace of technology's advancements is ever-increasing and intelligent systems, such as those found in robots and vehicles, have become larger and more complex. These intelligent systems have a heterogeneous structure, comprising a mixture of modules such as artificial intelligence (AI) and powertrain control modules that facilitate large-scale numerical calculation and real-time periodic processing functions. Information technology expert Professor Masato Edahiro, from the Graduate School of Informatics at the Nagoya University in Japan, explains that concurrent advances in semiconductor research have led to the miniaturisation of semiconductors, allowing a greater number of processors to be mounted on a single chip, increasing potential processing power. 'In addition to general-purpose processors such as CPUs, a mixture of multiple types of accelerators such as GPGPU and FPGA has evolved, producing a more complex and heterogeneous computer architecture,' he says. Edahiro and his partners have been working on the eMBP, a model-based parallelizer (MBP) that offers a mapping system as an efficient way of automatically generating parallel code for multi- and many-core systems. This ensures that once the hardware description is written, eMBP can bridge the gap between software and hardware to ensure that not only is an efficient ecosystem achieved for hardware vendors, but the need for different software vendors to adapt code for their particular platforms is also eliminated.


2020 ◽  
Vol 8 (4) ◽  
pp. 154-159
Author(s):  
Kamaran H.A Faraj ◽  
Asan B. Kanbar ◽  
Jaza Gul-Mohammed ◽  
Wafaa M. Hmeed ◽  
Shagul F. Karim

Since the traditional time loading (TTL) very primitive before the era of information communication technology (ICT) and it was really not depended on the result of time-loading due to the old version of computer architecture (i.e. serial processing). Nevertheless, the parallel processing systems open a wide area of researching for electronic time loading (ETL) over different operating systems by programing languages (i.e. python or private home page (Php)). The electronic time loading (ETL) for cloud Computing (CC) is a hot experimental topic.  ETL for CC is not only one parameter (i.e. a web technologies type or a web applications type or an infrastructures type or an architectures type). Moderately, the term CC refers to the evolution of the information technology (IT). As we realized the ETL is very important for reducing time wasting. The reducing time-waste loading over different web operating systems or CC is a target in this paper.  Finally, this paper test the Electronic Loading Time of CC over different operating systems with different types of network (i.e. public and private) discovering the least ETL. Hence the benchmarking TTL is not applicable (N/A) due to the activity from a person to others is very changeable and not depended on it at all.  This paper shows the total time and load time over different OS in seconds, and find out the least time loading required this work is a good solution of the response time over different operating system in open source-LOS and non-open source WOS.


2014 ◽  
Vol 68 (3) ◽  
pp. 1141-1162 ◽  
Author(s):  
Simon Holmbacka ◽  
Mohammad Fattah ◽  
Wictor Lund ◽  
Amir-Mohammad Rahmani ◽  
Sébastien Lafond ◽  
...  

2010 ◽  
Vol 47 (2) ◽  
pp. 120-131 ◽  
Author(s):  
Janez Puhan ◽  
Árpád Bűrmen ◽  
Tadej Tuma ◽  
Iztok Fajfar

The paper discusses whether (and how) to teach assembly coding as opposed to (or in conjunction with) higher programming languages as part of a modern electrical engineering curriculum. We describe the example of a very simple cooperative embedded real-time operating system, first programmed in C and then in assembler. A few lines of C language code are compared with the slightly longer assembly code equivalent, and the advantages and drawbacks are discussed. The example affords students a much deeper understanding of computer architecture and operating systems. The course is linked to other courses in the curriculum, which all use the same hardware and software platform; this lowers prices, reduces overheads and encourages students to reuse parts of a written code in subsequent courses. A student learns that badly written and poorly documented code is very difficult to reuse.


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