Design of low power based VLSI architecture for constant multiplier and high speed implementation using retiming technique

2016 ◽  
Author(s):  
S Jalaja ◽  
A M Vijaya Prakash
Keyword(s):  
Low Power ◽  
High Speed ◽  
Vlsi Architecture ◽  
Constant Multiplier ◽  
Retiming Technique

scholarly journals An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

2015 ◽  
Vol 2015 ◽  
pp. 1-13 ◽  
Author(s):  
T. Kalavathi Devi ◽  
Sakthivel Palaniappan
Keyword(s):  
Low Power ◽  
Communication Systems ◽  
High Speed ◽  
High Performance ◽  
Large Scale ◽  
Forward Error Correction ◽  
Vlsi Architecture ◽  
Convolutional Codes ◽  
Viterbi Decoder ◽  
Asynchronous Design

Convolutional codes are comprehensively used as Forward Error Correction (FEC) codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present, the design of a competent system in Very Large Scale Integration (VLSI) technology requires these VLSI parameters to be finely defined. The proposed asynchronous method focuses on reducing the power consumption of Viterbi decoder for various constraint lengths using asynchronous modules. The asynchronous designs are based on commonly used Quasi Delay Insensitive (QDI) templates, namely, Precharge Half Buffer (PCHB) and Weak Conditioned Half Buffer (WCHB). The functionality of the proposed asynchronous design is simulated and verified using Tanner Spice (TSPICE) in 0.25 µm, 65 nm, and 180 nm technologies of Taiwan Semiconductor Manufacture Company (TSMC). The simulation result illustrates that the asynchronous design techniques have 25.21% of power reduction compared to synchronous design and work at a speed of 475 MHz.

scholarly journals VLSI Architecture of High Performance Multiplier for High Speed Applications

2020 ◽  
Vol 9 (3) ◽  
pp. 442-445
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Vlsi Design ◽  
Vlsi Architecture ◽  
Digital Signal ◽  
Full Adder ◽  
Vital Role ◽  
Path Delay

In the application of digital signal process multipliers play a vital role. With advances in technology, several researchers have tried and try to design multipliers which supply high speed, low power consumption, regularity of layout and thus less space or maybe combination of them in one multiplier factor. Thus, Compact VLSI design for four bit multiplier factor is planned during this paper that is appropriate for low power and high speed applications. Multiplier factor with high performance is achieved through the novel style of hybrid single bit full adder and Dadda algorithmic rule. The important path delay and power consumption of the planned multiplier factor square measure reduced by 65.9% and 24.5% severally when put next with existing multipliers. The planned multiplier factor is synthesized exploitation CADENCE five.1.0 EDA tool and simulated exploitation spectre virtuoso.

scholarly journals Implementation of Vedic Multiplier and Floating Point Matrix Multiplier in Image Compression Applications

2020 ◽  
Vol 9 (2S5) ◽  
pp. 7-9
Keyword(s):  
Image Compression ◽  
Low Power ◽  
High Speed ◽  
Digital Images ◽  
Vlsi Architecture ◽  
Floating Point ◽  
Vedic Multiplier ◽  
The Matrix

It is implemented into low Power Verilog Architecture to the area for digital images Process application, In the matrix multiplications are one of the key arithmetically operations. And the constructed into VLSI architecture for Low Power, High Speed & Lowarea, Matrices Multiplications designed into become rare. In the projects, is a simple work of fiction in Verilog architectures with Floating point matrix multiplier be presents. The designs into consider as Pseudo codes with the matrix multiplications, CSD multiplication algorithms with power reductions, Convention floating points as number formatting & Pipeline concept with as improves speeds. In the Floating point matrix multiplier design as appropriate with anyone orbitrary sizes of the matrix among the followed matrices rule. It is designed may also gives as higher precision outputs. The simulation result is perfect matched into the MATLAB result.

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