Lazy release consistency for GPUs

Author(s):  
Johnathan Alsop ◽  
Marc S. Orr ◽  
Bradford M. Beckmann ◽  
David A. Wood
Keyword(s):  
1989 ◽  
Vol 5 (3) ◽  
pp. 308-323 ◽  
Author(s):  
Glenn S. Wunderly ◽  
Maury L. Hull

A new approach to ski binding design is advanced. It begins with a release locus derived from injury mechanics research and knowledge of the expected loading conditions and then incorporates these into the final binding design. A mechanical ski binding designed by following the new approach is presented. This binding offers a number of performance features not found in commercially available designs. One feature is the ability to eliminate the axial force supported by the tibial shaft from affecting release in forward bending. A second feature is the binding’s ability to release according to virtually any preprogrammed locus of the combination of moments in both bending and torsion. A third feature is a release mechanism that is insensitive to the common frictional forces that affect the release consistency of conventional heel/toe bindings. In addition to these features, the binding offers a variety of operational conveniences. The presentation of the binding not only describes the design details but also evaluates the release performance (i.e., locus and consistency) based upon laboratory tests under quasistatic loading.


2001 ◽  
Vol 11 (01) ◽  
pp. 65-76
Author(s):  
LUCIANA ARANTES ◽  
DENIS POITRENAUD ◽  
PIERRE SENS ◽  
BERTIL FOLLIOT

In this article, we introduce a new logical clock, the barrier-lock clock, whose conception is based on the lazy release consistency memory model (LRC) supported by several distributed shared memory (DSM) systems. Since in the LRC, the propagation of shared memory updates performed by the processes of a parallel application is induced by lock and barrier operations, our logical clock has been modeled on those operations. Each barrier-lock times-tamp encodes the synchronization operation with which it is associated. Its size is not dependent on the number of processes of the system, as the traditional logical vector clocks, but it is proportional to the number of locks. The barrier-lock time characterizes the causality of shared memory updates performed by processes of a parallel application running on a LRC-based DSM system. A formal proof and experimental tests have confirmed such property.


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