A Code Partitioning Tool for Simulink Models to Implement on FPGA-Based Network-on-Chip Architecture

2014 ◽  
Author(s):  
Satoru Miyasono ◽  
Yosuke Moriai ◽  
Hiroshi Saito
Keyword(s):  
Network On Chip ◽  
On Chip ◽  
Code Partitioning

Pre-allocated Path Based Low Latency Router Architecture for Network-on-chip

2014 ◽  
Vol 35 (2) ◽  
pp. 341-346
Author(s):  
Xiao-fu Zheng ◽  
Hua-xi Gu ◽  
Yin-tang Yang ◽  
Zhong-fan Huang
Keyword(s):  
Network On Chip ◽  
Low Latency ◽  
Router Architecture ◽  
On Chip

scholarly journals On the Cooperative Relaying Strategies for Multi-Core Wireless Network-on-Chip

IEEE Access ◽  
2021 ◽  
pp. 1-1
Author(s):  
Quoc-Tuan Vien ◽  
Michael Opoku Agyeman ◽  
Mallik Tatipamula ◽  
Huan X. Nguyen
Keyword(s):  
Wireless Network ◽  
Network On Chip ◽  
Cooperative Relaying ◽  
On Chip ◽  
Relaying Strategies

scholarly journals Self-Healing Router Approach for High-Performance Network-on-Chip

2021 ◽  
Vol 2 ◽  
pp. 485-496
Author(s):  
Kasem Khalil ◽  
Omar Eldash ◽  
Ashok Kumar ◽  
Magdy Bayoumi
Keyword(s):  
High Performance ◽  
Network On Chip ◽  
Self Healing ◽  
On Chip
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