GRAPE-MPs: Implementation of an SIMD for Quadruple/Hexuple/Octuple-Precision Arithmetic Operation on a Structured ASIC and an FPGA

2012 ◽  
Author(s):  
Naohito Nakasato ◽  
Hiroshi Daisaka ◽  
Toshiyuki Fukushige ◽  
Atsushi Kawai ◽  
Junichiro Makino ◽  
...  
Keyword(s):  
Arithmetic Operation

User Dependent Handwriting Recognition using off-line OCR for Arithmetic Operation and Text Processing

2011 ◽  
Vol 6 (1) ◽  
pp. 28-35
Author(s):  
D.P. Gaikwad ◽  
Yogesh Gunge ◽  
Raghunandan Mundada ◽  
Himani Bharadwaj ◽  
Swapnil Patil
Keyword(s):  
Text Processing ◽  
Handwriting Recognition ◽  
Arithmetic Operation

Error-aware Design Procedure to Implement Energy-efficient Approximate Squaring Hardware

2020 ◽  
Vol 10 (4) ◽  
pp. 471-477
Author(s):  
Merin Loukrakpam ◽  
Ch. Lison Singh ◽  
Madhuchhanda Choudhury
Keyword(s):  
Energy Saving ◽  
Relative Error ◽  
Energy Efficient ◽  
Piecewise Linear ◽  
Arithmetic Operation ◽  
Design Procedure ◽  
Digital Signal ◽  
Maximum Relative Error ◽  
Square Function ◽  
Efficient Design

Background:: In recent years, there has been a high demand for executing digital signal processing and machine learning applications on energy-constrained devices. Squaring is a vital arithmetic operation used in such applications. Hence, improving the energy efficiency of squaring is crucial. Objective:: In this paper, a novel approximation method based on piecewise linear segmentation of the square function is proposed. Methods: Two-segment, four-segment and eight-segment accurate and energy-efficient 32-bit approximate designs for squaring were implemented using this method. The proposed 2-segment approximate squaring hardware showed 12.5% maximum relative error and delivered up to 55.6% energy saving when compared with state-of-the-art approximate multipliers used for squaring. Results: The proposed 4-segment hardware achieved a maximum relative error of 3.13% with up to 46.5% energy saving. Conclusion:: The proposed 8-segment design emerged as the most accurate squaring hardware with a maximum relative error of 0.78%. The comparison also revealed that the 8-segment design is the most efficient design in terms of error-area-delay-power product.

scholarly journals Fast Two-Stage Computation of an Index Policy for Multi-Armed Bandits with Setup Delays

Mathematics ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 52
Author(s):  
José Niño-Mora
Keyword(s):  
Numerical Study ◽  
Arithmetic Operation ◽  
Bandit Problem ◽  
Index Policy ◽  
Two Stage ◽  
Second Stage ◽  
Whittle Index ◽  
Set Up ◽  
Computing Method ◽  
Special Case

We consider the multi-armed bandit problem with penalties for switching that include setup delays and costs, extending the former results of the author for the special case with no switching delays. A priority index for projects with setup delays that characterizes, in part, optimal policies was introduced by Asawa and Teneketzis in 1996, yet without giving a means of computing it. We present a fast two-stage index computing method, which computes the continuation index (which applies when the project has been set up) in a first stage and certain extra quantities with cubic (arithmetic-operation) complexity in the number of project states and then computes the switching index (which applies when the project is not set up), in a second stage, with quadratic complexity. The approach is based on new methodological advances on restless bandit indexation, which are introduced and deployed herein, being motivated by the limitations of previous results, exploiting the fact that the aforementioned index is the Whittle index of the project in its restless reformulation. A numerical study demonstrates substantial runtime speed-ups of the new two-stage index algorithm versus a general one-stage Whittle index algorithm. The study further gives evidence that, in a multi-project setting, the index policy is consistently nearly optimal.

scholarly journals Multiple-Precision BLAS Library for Graphics Processing Units

2020 ◽  
Author(s):  
Konstantin Isupov ◽  
Vladimir Knyazkov
Keyword(s):  
Graphics Processing Units ◽  
Arithmetic Operation ◽  
Number System ◽  
Residue Number System ◽  
Floating Point ◽  
Data Types ◽  
Rounding Errors ◽  
Multiple Precision ◽  
Graphics Processing ◽  
Point Arithmetic

The binary32 and binary64 floating-point formats provide good performance on current hardware, but also introduce a rounding error in almost every arithmetic operation. Consequently, the accumulation of rounding errors in large computations can cause accuracy issues. One way to prevent these issues is to use multiple-precision floating-point arithmetic. This preprint, submitted to Russian Supercomputing Days 2020, presents a new library of basic linear algebra operations with multiple precision for graphics processing units. The library is written in CUDA C/C++ and uses the residue number system to represent multiple-precision significands of floating-point numbers. The supported data types, memory layout, and main features of the library are considered. Experimental results are presented showing the performance of the library.

scholarly journals A Singular Value Thresholding with Diagonal-Update Algorithm for Low-Rank Matrix Completion

2020 ◽  
Vol 2020 ◽  
pp. 1-14
Author(s):  
Yong-Hong Duan ◽  
Rui-Ping Wen ◽  
Yun Xiao
Keyword(s):  
Matrix Completion ◽  
Arithmetic Operation ◽  
Computational Cost ◽  
Singular Value ◽  
Low Rank ◽  
Simple Arithmetic ◽  
Rank Matrix ◽  
Low Rank Matrix Completion ◽  
Low Rank Matrix ◽  
Singular Value Thresholding

The singular value thresholding (SVT) algorithm plays an important role in the well-known matrix reconstruction problem, and it has many applications in computer vision and recommendation systems. In this paper, an SVT with diagonal-update (D-SVT) algorithm was put forward, which allows the algorithm to make use of simple arithmetic operation and keep the computational cost of each iteration low. The low-rank matrix would be reconstructed well. The convergence of the new algorithm was discussed in detail. Finally, the numerical experiments show the effectiveness of the new algorithm for low-rank matrix completion.

scholarly journals Motion Control Algorithm Expanding Arithmetic Operation for Low-Cost Microprocessor

2012 ◽  
Vol 18 (12) ◽  
pp. 1079-1085
Author(s):  
Sang-Chan Moon ◽  
Jae-Jun Kim ◽  
Kyu-Min Nam ◽  
Byoung-Soo Kim ◽  
Soon-Geul Lee
Keyword(s):  
Motion Control ◽  
Control Algorithm ◽  
Low Cost ◽  
Arithmetic Operation

scholarly journals Design of delay efficient Booth multiplier using pipelining

2018 ◽  
Vol 7 (2.16) ◽  
pp. 94
Author(s):  
Abhishek Choubey ◽  
SPV Subbarao ◽  
Shruti B. Choubey
Keyword(s):  
Critical Path ◽  
Arithmetic Operation ◽  
Vlsi Design ◽  
Digital Signal ◽  
Path Delay ◽  
Large Area ◽  
Booth Multiplier ◽  
Critical Path Delay ◽  
Long Latency ◽  
Comparison Results

Multiplication is one of the most an essential arithmetic operation used in numerous applications in digital signal processing and communications. These applications need transformations, convolutions and dot products that involve an enormous amount of multiplications of an operand with a constant. Typical examples include wavelet, digital filters, such as FIR or IIR. However, multiplier structures have relatively large area-delay product, long latency and significantly high power consumption compared to other the arithmetic structure. Therefore, low power multiplier design has been always a significant part of DSP structure for VLSI design. The Booth multiplier is promising as the most efficient amongst the others multiplier as it reduces the complexity of considerably than others. In this paper, we have proposed Booth-multiplier using seamless pipelining. Theoretical comparison results show that the proposed Booth multiplier requires less critical path delay compared to traditional Booth multiplier. ASIC simulation results show proposed radix-16 Booth multiplier 13% less critical path delay for word width n=16 and 17% less critical path delay compared for bit width n=32 to best existing radix-16 Booth multiplier. 

scholarly journals Design and Analysis of High Speed Low Power Hybrid Adder Using Transmission Gates

2016 ◽  
Vol 5 (03) ◽  
pp. 07-12
Author(s):  
Prof. Amruta Bijwar
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Arithmetic Operation ◽  
Vlsi Design ◽  
Full Adder ◽  
Basic Component ◽  
Xnor Gate ◽  
Transmission Gates ◽  
Design Systems ◽  
Complex Circuits

Addition is the vital arithmetic operation and it acts as a base for many arithmetic operations such as multipliers, dividers, etc. A full adder acts as a basic component in complex circuits. Full adder is the essential segment in many applications such as DSP, Microcontroller, Microprocessor, etc. There exists an inevitable swap between speed and power indulgence in VLSI design systems. A new modified hybrid 1-bit full adder using TG is presented. Here, the circuit is replaced with a simple XNOR gate, which increases the speed. Due to this, transistor count gets reduced results in better optimization of area. The analysis has been carried out also for 2, 4, 8 and 16 bit and it is compared with the various techniques. The result shows a significant improvement in speed, area, power dissipation and transistor counts.

scholarly journals The Role of Phonological and Visual Working Memory in Carry Operations or Intermediate Solutions in Complex Mental Arithmetic

2021 ◽  
Author(s):  
◽  
Wei Dai
Keyword(s):  
Working Memory ◽  
Change Detection ◽  
Visual Working Memory ◽  
Visual Processing ◽  
Mental Arithmetic ◽  
Arithmetic Operation ◽  
Phonological Working Memory ◽  
Mental Addition ◽  
Memory Resources

<p>The present research comprises four experiments designed to explore the role of visual and phonological working memory resources in carry operations or intermediate solutions in complex mental addition and multiplication. A special consideration was given to the effect of arithmetic operation on the relative involvement of visual and phonological resources in complex addition and multiplication.  A pilot study was conducted prior to the experiments, aiming to examine the suitability of visual and phonological stimuli for change detection and working memory capacity estimation. Two staff of Victoria University of Wellington with normal or corrected vision attended the pilot study as participants. Pilot Experiments 1 to 4 tested the suitability for probing visual working memory (VWM) capacity of two types of visual stimulus with different feature dimensions: bars of different orientations and Gabor patches with different orientations and spatial frequencies. A single-probe change-detection experimental paradigm was used, with participants making decisions about whether or not probe items were the same as memory items presented previously. Both presentation durations and set sizes were manipulated. Stable estimates of visual working memory capacities were found when Gabor patches with varied spatial frequencies were used, suggesting its utility as a probe for estimating visual working memory capacity. Pilot Experiment 5 was designed to examine the suitability of pronounceable consonant-vowel-consonant non-words as a probe of phonological working memory (PWM). Valid estimates of PWM capacity were found for both participants, suggesting the suitability of phonological non-words as phonological stimuli of assessing PWM capacities and interfering with information phonologically-represented and maintained in working memory.  Experiments 1 to 4 investigated the relative involvement of visual and phonological working memory resources in carry operations or intermediate solutions in mental addition and multiplication. Fifty-six undergraduate students of Victoria University of Wellington participated all experiments, and 48 of them provided valid data for final analysis. A dual-task interference paradigm was used in all experiments, with arithmetic tasks and visual/phonological change-detection tasks either performed alone, or simultaneously. For arithmetic tasks, double-digit addition problems and multiplication problems comprising one single-digit and one double-digit were presented horizontally and continuously, and participants reported the final solutions verbally. For visual change-detection tasks, study items were visually presented to participants for 1,000ms before they disappeared. After a 4000ms retention interval, a probe item was presented and participants judged whether the probe item was the same as one of the memory items. For phonological change-detection tasks, phonological nonwords were verbally presented to participants sequentially. After a 4000ms retention interval, a probe nonword was presented to participants, and they indicated whether or not the probe was the same as one of the study non-words. Both numbers of carry operations involved in the arithmetic problems (zero, one, and two) and levels of visual/phonological loads (low, medium, and high) were manipulated in all experiments.   For all experiments, the effect of the number of carry operations on calculation performance was observed: arithmetic problems involving more carry operations were solved less rapidly and accurately. This effect was enlarged by concurrent visual and phonological loads, evidenced by significant interactions between task conditions and number of carry operations observed in the accuracy analyses of the arithmetic tasks in all experiments except Experiment 2, in which multiplication problems were solved under visual loads. These findings suggest that both visual and phonological resources are required for the temporary storage of intermediate solutions or carry information in mental addition, while for mental multiplication, only evidence for a role of phonological representations in carry operations was found.  For all experiments, the greater performance impairment of carry problems than no-carry problems associated with the presence of working memory loads was not further increased by increasing load level: There were no significant three-way interactions between task conditions, number of carry operations and load levels in accuracy analyses of arithmetic tasks. One possible explanation for this absence of significant three-way interactions might be attributable to some participants switching between phonological and visual working memory for the temporary storage of carrier information or intermediate solutions as a result of decreasing amount of available phonological or visual working memory resources.  In conclusion, the findings of the present research provide support for a role of both visual and phonological working memory resources in carry operations in mental addition, and a role of phonological working memory resources in carry operation in mental multiplication. Thus, it can be concluded that solving mental arithmetic problems involving carry-operations requires working memory resources. However, these results contradict the prediction of the Triple Code Model, which assumes addition mainly relies on visual processing, and multiplication mainly relies on verbal processing, while complex mental arithmetic is solved with the aid of visual processing regardless of the arithmetic operation. Thus, these results challenge the operation-specific involvement of working memory resources in complex mental arithmetic. However, it should be noted that the same arithmetic problems were solved three times by the same participants, which might have encouraged more activation in phonological processing than visual processing due to the practice effect.</p>

Group decision making method for residents to choose livable cities depicted by n-intuitionistic polygonal fuzzy sets1

2020 ◽  
Vol 39 (3) ◽  
pp. 3503-3518
Author(s):  
Guijun Wang ◽  
Jie Zhou
Keyword(s):  
Decision Making ◽  
Group Decision Making ◽  
Fuzzy Set ◽  
Group Decision ◽  
Arithmetic Operation ◽  
Intuitionistic Fuzzy Set ◽  
Score Function ◽  
Fuzzy Information ◽  
Decision Matrix ◽  
Arithmetic Average

The polygonal fuzzy set is an effective tool to express a class of fuzzy information with the help of finite ordered real numbers. It can not only guarantee the closeness of arithmetic operation of the polygonal fuzzy sets, but also has good linearity and intuitiveness. Firstly, the concept of the n-intuitionistic polygonal fuzzy set (n-IPFS) is proposed based on the intuitionistic fuzzy set and the polygonal fuzzy set. The ordered representation and arithmetic operation of n-IPFS are given by an example. Secondly, a new aggregation method for multi attribute fuzzy information is given based on the n-IPFS operations and the weighted arithmetic average operator, and the ranking criteria of n-IPFS are obtained by using the score function and the accuracy function. Finally, a new group decision making method is proposed for urban residents to choose the livable city problem based on the decision matrix of the n-IPFS, and the effectiveness of the proposed method is explained by an actual example.

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