Why Computer Architecture Matters: Memory Access

2008 ◽  
Vol 10 (4) ◽  
pp. 71-75 ◽  
Author(s):  
Cosmin Pancratov ◽  
Jacob M. Kurzer ◽  
Kelly A. Shaw ◽  
Matthew L. Trawick
Keyword(s):  
Computer Architecture ◽  
Memory Access

scholarly journals Memory Access Optimization of a Neural Network Accelerator Based on Memory Controller

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 438
Author(s):  
Rongshan Wei ◽  
Chenjia Li ◽  
Chuandong Chen ◽  
Guangyu Sun ◽  
Minghua He
Keyword(s):  
Neural Network ◽  
Computer Architecture ◽  
Random Access ◽  
Mapping Method ◽  
Memory Access ◽  
Hardware Accelerators ◽  
Great Success ◽  
Memory Controller ◽  
Access Latency ◽  
Address Mapping

Special accelerator architecture has achieved great success in processor architecture, and it is trending in computer architecture development. However, as the memory access pattern of an accelerator is relatively complicated, the memory access performance is relatively poor, limiting the overall performance improvement of hardware accelerators. Moreover, memory controllers for hardware accelerators have been scarcely researched. We consider that a special accelerator memory controller is essential for improving the memory access performance. To this end, we propose a dynamic random access memory (DRAM) memory controller called NNAMC for neural network accelerators, which monitors the memory access stream of an accelerator and transfers it to the optimal address mapping scheme bank based on the memory access characteristics. NNAMC includes a stream access prediction unit (SAPU) that analyzes the type of data stream accessed by the accelerator via hardware, and designs the address mapping for different banks using a bank partitioning model (BPM). The image mapping method and hardware architecture were analyzed in a practical neural network accelerator. In the experiment, NNAMC achieved significantly lower access latency of the hardware accelerator than the competing address mapping schemes, increased the row buffer hit ratio by 13.68% on average (up to 26.17%), reduced the system access latency by 26.3% on average (up to 37.68%), and lowered the hardware cost. In addition, we also confirmed that NNAMC efficiently adapted to different network parameters.

Adaptive Signal Analysis and Interpretation for Real-time Intelligent Patient Monitoring

1994 ◽  
Vol 33 (01) ◽  
pp. 60-63 ◽  
Author(s):  
E. J. Manders ◽  
D. P. Lindstrom ◽  
B. M. Dawant
Keyword(s):  
Computer Architecture ◽  
Real Time ◽  
Data Abstraction ◽  
Monitoring Strategy ◽  
Intelligent Monitoring ◽  
Patient Status ◽  
On Line ◽  
Main Components ◽  
And Control ◽  
Adaptive Signal

Abstract:On-line intelligent monitoring, diagnosis, and control of dynamic systems such as patients in intensive care units necessitates the context-dependent acquisition, processing, analysis, and interpretation of large amounts of possibly noisy and incomplete data. The dynamic nature of the process also requires a continuous evaluation and adaptation of the monitoring strategy to respond to changes both in the monitored patient and in the monitoring equipment. Moreover, real-time constraints may imply data losses, the importance of which has to be minimized. This paper presents a computer architecture designed to accomplish these tasks. Its main components are a model and a data abstraction module. The model provides the system with a monitoring context related to the patient status. The data abstraction module relies on that information to adapt the monitoring strategy and provide the model with the necessary information. This paper focuses on the data abstraction module and its interaction with the model.

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