Ultra-low power monolithically integrated InGaAs/GaAs phototransceiver incorporating a modulated barrier photodiode and a quantum dot microcavity LED

2002 ◽  
Author(s):  
O. Qasaimeh ◽  
W. Zhou ◽  
P. Bhattacharya ◽  
D. Huffaker ◽  
D. Deppe
Keyword(s):  
Quantum Dot ◽  
Low Power ◽  
Ultra Low Power ◽  
Monolithically Integrated

Monolithically integrated low-power phototransceiver incorporating InGaAs/GaAs quantum-dot microcavity LED and modulated barrier photodiode

2000 ◽  
Vol 36 (23) ◽  
pp. 1955 ◽  
Author(s):  
O. Qasaimeh ◽  
W.-D. Zhou ◽  
P. Bhattacharya ◽  
D. Huffaker ◽  
D.G. Deppe
Keyword(s):  
Quantum Dot ◽  
Low Power ◽  
Monolithically Integrated ◽  
Gaas Quantum Dot

scholarly journals A Ultra-Low-Power FPGA Based on Monolithically Integrated RRAMs

2015 ◽  
Author(s):  
Pierre-Emmanuel Gaillardon ◽  
Xifan Tang ◽  
Jury Sandrini ◽  
Maxime Thammasack ◽  
Somayyeh Rahimian Omam ◽  
...  
Keyword(s):  
Low Power ◽  
Ultra Low Power ◽  
Monolithically Integrated

Design & Analysis of Novel Non-Reversible & Reversible Parity Generator & Detector in Quantum Cellular Automata using Feynman Gate

2021 ◽  
Vol 13 ◽  
Author(s):  
Neeraj Tripathi ◽  
Mohammad Mudakir Fazili ◽  
Rahil Jahangir
Keyword(s):  
Energy Dissipation ◽  
Cellular Automata ◽  
Quantum Dot ◽  
Low Power ◽  
Fault Tolerant ◽  
Design Parameters ◽  
Logic Function ◽  
Ultra Low Power ◽  
Quantum Dot Cellular Automata ◽  
Parity Generator

Aim: A novel design for non-reversible as well as reversible parity generator and detector in Quantum-dot Cellular Automata (QCA) technology is presented in this research article. Parity generator and detector circuits are reliable error-checking components of a nano-communication system. Objective: The main focus of this research is to design an ultra-low-power fault-tolerant reversible gate implementation of the parity logic function in QCA. An efficient QCA design layout with minimal area, less latency and the least energy dissipation is desired. Methods: The proposed designs are developed using Quantum-dot Cellular Automata (QCA) technology. The circuits are optimized using majority gate reduction and clock zone reduction techniques. Also, the cell-cell interaction technique is employed to further optimize the QCA circuit. To increase the fault tolerance and for ultra-low power operation, reversible QCA circuits are designed using cascaded Feynman gates. Results and Conclusion: The efficiency of the parity generator and detector is calculated to be more than 25% compared to existing QCA layouts. It is demonstrated in this paper that the proposed circuits perform exceptionally well on every design parameter. The design parameters under consideration are cell count, cell area, complexity, crossover count, latency and energy dissipation. Using reversible logic, a fault-tolerant and defect-sensitive circuit is developed for parity generation and detection.

Sign in / Sign up

Export Citation Format

Share Document