Interconnect Design and Benchmarking for Charge-Based Beyond-CMOS Device Proposals

2016 ◽  
Vol 37 (4) ◽  
pp. 508-511 ◽  
Author(s):  
Chenyun Pan ◽  
Azad Naeemi
Keyword(s):  
Interconnect Design ◽  
Beyond Cmos

Neural-based Transient Behavioral Modeling of IC Buffers for High-speed Interconnect Design

PIERS Online ◽  
2007 ◽  
Vol 3 (7) ◽  
pp. 1136-1138
Author(s):  
Yi Cao ◽  
Qijun Zhang ◽  
Ihsan Erdin
Keyword(s):  
High Speed ◽  
Behavioral Modeling ◽  
Interconnect Design

scholarly journals A RF Redundant TSV Interconnection for High Resistance Si Interposer

Micromachines ◽  
2021 ◽  
Vol 12 (2) ◽  
pp. 169
Author(s):  
Mengcheng Wang ◽  
Shenglin Ma ◽  
Yufeng Jin ◽  
Wei Wang ◽  
Jing Chen ◽  
...  
Keyword(s):  
Millimeter Wave ◽  
High Frequency ◽  
High Performance ◽  
Rapid Development ◽  
Coplanar Waveguide ◽  
Equivalent Circuit Model ◽  
High Resistivity ◽  
Performance Requirements ◽  
Wave Radar ◽  
Interconnect Design

Through Silicon Via (TSV) technology is capable meeting effective, compact, high density, high integration, and high-performance requirements. In high-frequency applications, with the rapid development of 5G and millimeter-wave radar, the TSV interposer will become a competitive choice for radio frequency system-in-package (RF SIP) substrates. This paper presents a redundant TSV interconnect design for high resistivity Si interposers for millimeter-wave applications. To verify its feasibility, a set of test structures capable of working at millimeter waves are designed, which are composed of three pieces of CPW (coplanar waveguide) lines connected by single TSV, dual redundant TSV, and quad redundant TSV interconnects. First, HFSS software is used for modeling and simulation, then, a modified equivalent circuit model is established to analysis the effect of the redundant TSVs on the high-frequency transmission performance to solidify the HFSS based simulation. At the same time, a failure simulation was carried out and results prove that redundant TSV can still work normally at 44 GHz frequency when failure occurs. Using the developed TSV process, the sample is then fabricated and tested. Using L-2L de-embedding method to extract S-parameters of the TSV interconnection. The insertion loss of dual and quad redundant TSVs are 0.19 dB and 0.46 dB at 40 GHz, respectively.

Brain-Inspired Computing: Adventure from Beyond CMOS Technologies to Beyond von Neumann Architectures ICCAD Special Session Paper

2021 ◽  
Author(s):  
Hussam Amrouch ◽  
Jian-Jia Chen ◽  
Kaushik Roy ◽  
Yuan Xie ◽  
Indranil Chakraborty ◽  
...  
Keyword(s):  
Special Session ◽  
Von Neumann ◽  
Session Paper ◽  
Beyond Cmos

scholarly journals Physical Simulations of High Speed and Low Power NanoMagnet Logic Circuits

2018 ◽  
Vol 8 (4) ◽  
pp. 37 ◽  
Author(s):  
Giovanna Turvani ◽  
Laura D’Alessandro ◽  
Marco Vacca
Keyword(s):  
High Speed ◽  
Logic Circuits ◽  
Micromagnetic Simulations ◽  
Electrical Fields ◽  
Nanomagnet Logic ◽  
Nanomagnetic Logic ◽  
Elastic Effect ◽  
Physical Simulations ◽  
A Chain ◽  
Beyond Cmos

Among all “beyond CMOS” solutions currently under investigation, nanomagnetic logic (NML) technology is considered to be one of the most promising. In this technology, nanoscale magnets are rectangularly shaped and are characterized by the intrinsic capability of enabling logic and memory functions in the same device. The design of logic architectures is accomplished by the use of a clocking mechanism that is needed to properly propagate information. Previous works demonstrated that the magneto-elastic effect can be exploited to implement the clocking mechanism by altering the magnetization of magnets. With this paper, we present a novel clocking mechanism enabling the independent control of each single nanodevice exploiting the magneto-elastic effect and enabling high-speed NML circuits. We prove the effectiveness of this approach by performing several micromagnetic simulations. We characterized a chain of nanomagnets in different conditions (e.g., different distance among cells, different electrical fields, and different magnet geometries). This solution improves NML, the reliability of circuits, the fabrication process, and the operating frequency of circuits while keeping the energy consumption at an extremely low level.

A Survey on Architecture Advances Enabled by Emerging Beyond-CMOS Technologies

2019 ◽  
Vol 36 (3) ◽  
pp. 46-68 ◽  
Author(s):  
An Chen ◽  
Supriyo Datta ◽  
X. Sharon Hu ◽  
Michael T. Niemier ◽  
Tajana Simunic Rosing ◽  
...  
Keyword(s):  
Beyond Cmos
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