Speeding-Up Simulation-Based Fault Injection of Complex HDL Models

2016 ◽  
Author(s):  
Ilya Tuzov ◽  
Juan-Carlos Ruiz ◽  
David De Andres ◽  
Pedro Gil
Keyword(s):  
Fault Injection ◽  
Simulation Based

scholarly journals Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2074
Author(s):  
J.-Carlos Baraza-Calvo ◽  
Joaquín Gracia-Morán ◽  
Luis-J. Saiz-Adalid ◽  
Daniel Gil-Tomás ◽  
Pedro-J. Gil-Vicente
Keyword(s):  
Fault Tolerance ◽  
Error Correction ◽  
Error Detection ◽  
Fault Injection ◽  
Error Correction Codes ◽  
Transient Faults ◽  
Tolerance Mechanism ◽  
Intermittent Faults ◽  
Risc Processor ◽  
Simulation Based

Due to transistor shrinking, intermittent faults are a major concern in current digital systems. This work presents an adaptive fault tolerance mechanism based on error correction codes (ECC), able to modify its behavior when the error conditions change without increasing the redundancy. As a case example, we have designed a mechanism that can detect intermittent faults and swap from an initial generic ECC to a specific ECC capable of tolerating one intermittent fault. We have inserted the mechanism in the memory system of a 32-bit RISC processor and validated it by using VHDL simulation-based fault injection. We have used two (39, 32) codes: a single error correction–double error detection (SEC–DED) and a code developed by our research group, called EPB3932, capable of correcting single errors and double and triple adjacent errors that include a bit previously tagged as error-prone. The results of injecting transient, intermittent, and combinations of intermittent and transient faults show that the proposed mechanism works properly. As an example, the percentage of failures and latent errors is 0% when injecting a triple adjacent fault after an intermittent stuck-at fault. We have synthesized the adaptive fault tolerance mechanism proposed in two types of FPGAs: non-reconfigurable and partially reconfigurable. In both cases, the overhead introduced is affordable in terms of hardware, time and power consumption.

An Implementation of Simulation-Based Environment for Bus Fault Injection Techniques

2013 ◽  
Vol 756-759 ◽  
pp. 4672-4676
Author(s):  
Biao Biao Shi ◽  
Xiao Peng Gao
Keyword(s):  
Fault Injection ◽  
Low Cost ◽  
Injection System ◽  
Simulation Based ◽  
Injection Techniques ◽  
Software Implementations ◽  
Cost Simulation ◽  
Validation Technique ◽  
Complex Computer ◽  
Design Experiments

Reliability is the most important feature in this more and more complex computer system era. Fault injection is dependability validation technique to evaluating the system. Hardware and Software implementations of fault injection have a long history and are much more mature than simulated fault injection. In this paper, we compare the differences between these three types of fault injections at first. Then, we identify and understand the types of fault. We design a low-cost, simulation-based fault injection system and design experiments to verify the correctness.

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