scholarly journals Multilevel Cache Modeling for Chip-Multiprocessor Systems

2011 ◽  
Vol 10 (2) ◽  
pp. 49-52 ◽  
Author(s):  
Pablo Prieto ◽  
Valentin Puente ◽  
Jose-Angel Gregorio
Keyword(s):  
Chip Multiprocessor ◽  
Multiprocessor Systems ◽  
Cache Modeling ◽  
Multilevel Cache

Dynamic I/O-Aware Scheduling for Batch-Mode Applications on Chip Multiprocessor Systems of Cluster Platforms

2014 ◽  
Vol 29 (1) ◽  
pp. 21-37 ◽  
Author(s):  
Fang Lv ◽  
Hui-Min Cui ◽  
Lei Wang ◽  
Lei Liu ◽  
Cheng-Gang Wu ◽  
...  
Keyword(s):  
Chip Multiprocessor ◽  
Multiprocessor Systems ◽  
Batch Mode ◽  
On Chip

EFFICIENT SCHEME FOR CONGESTION CONTROL IN NETWORK-ON-CHIP WITH QoS CONSIDERATION

2014 ◽  
Vol 23 (09) ◽  
pp. 1450120 ◽  
Author(s):  
ADEL SOUDANI ◽  
AHMED ALDAMMAS ◽  
ABDULLAH AL-DHELAAN
Keyword(s):  
Network On Chip ◽  
Chip Multiprocessor ◽  
Multiprocessor Systems ◽  
Signaling Mechanism ◽  
Qos Management ◽  
Efficient Scheme ◽  
High Bandwidth ◽  
On Chip ◽  
Internal Architecture

Embedded distributed multimedia applications based on the use of on-chip networks for communication and messages exchange requires specific and enhanced quality of service (QoS) management. To reach the desired performances at the application level, the network-on-chip (NoC) router should implement per flit handling strategy with wide granularity. This purpose requires an enhanced internal architecture that ensures from one hand a specific management according to a service classification and from the other hand, it enhances the routing process. In this context, this paper proposes a new mechanism for QoS management in NoC. This mechanism is based on the use of central memory where flits are in-queued according to their class of service. This scheme enables an optimal flit scheduling phase and provides more capabilities to drop low important flits when the router shows congestion state symptoms. The paper presents, also, a protocol structure that fills with this architecture and introduces a signaling mechanism to make efficient the QoS management through the proposed architecture. The circuit performances and its adaptability to achieve QoS with low power processing and high bandwidth in on chip multiprocessor systems will be studied in this paper.

Network-on-Chip virtualization in Chip-Multiprocessor Systems

2012 ◽  
Vol 58 (3-4) ◽  
pp. 126-139 ◽  
Author(s):  
Francisco Triviño ◽  
José L. Sánchez ◽  
Francisco J. Alfaro ◽  
José Flich
Keyword(s):  
Network On Chip ◽  
Chip Multiprocessor ◽  
Multiprocessor Systems ◽  
On Chip
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