scholarly journals A True Time Delay Beamforming System Incorporating a Wavelength Tunable Optical Phase-Lock Loop

2007 ◽  
Vol 25 (7) ◽  
pp. 1761-1770 ◽  
Author(s):  
Howard R. Rideout ◽  
Joe S. Seregelyi ◽  
Jianping Yao
Keyword(s):  
Time Delay ◽  
Phase Lock Loop ◽  
Phase Lock ◽  
Optical Phase ◽  
Wavelength Tunable ◽  
True Time Delay ◽  
True Time

Stable wavelength tunable fiber ring laser for true-time delay system

Laser Physics ◽  
2011 ◽  
Vol 21 (10) ◽  
pp. 1825-1828 ◽  
Author(s):  
X. L. Zhang ◽  
K. J. Zhou ◽  
Y. X. Luo
Keyword(s):  
Time Delay ◽  
Ring Laser ◽  
Delay System ◽  
Fiber Ring Laser ◽  
Time Delay System ◽  
Fiber Ring ◽  
Wavelength Tunable ◽  
True Time Delay ◽  
True Time

Silicon nanomembrane based photonic crystal waveguide array for wavelength-tunable true-time-delay lines

2012 ◽  
Vol 101 (5) ◽  
pp. 051101 ◽  
Author(s):  
Che-Yun Lin ◽  
Harish Subbaraman ◽  
Amir Hosseini ◽  
Alan X. Wang ◽  
Liang Zhu ◽  
...  
Keyword(s):  
Photonic Crystal ◽  
Time Delay ◽  
Waveguide Array ◽  
Delay Lines ◽  
Photonic Crystal Waveguide ◽  
Wavelength Tunable ◽  
True Time Delay ◽  
Silicon Nanomembrane ◽  
True Time

Influence of Time Delay on Pull-in Behaviour of Dither Optical Phase-Lock Loop

2018 ◽  
Vol 65 (5) ◽  
pp. 679-688
Author(s):  
Abhijit Banerjee ◽  
Baidyanath Biswas
Keyword(s):  
Time Delay ◽  
Phase Lock Loop ◽  
Phase Lock ◽  
Optical Phase

RF MEMS Extended Tuning Range Varactor and Varactor Based True Time Delay Line Design

PIERS Online ◽  
2008 ◽  
Vol 4 (4) ◽  
pp. 433-436 ◽  
Author(s):  
Yaping Liang ◽  
Calvin W. Domier ◽  
Neville C. Luhmann, Jr.
Keyword(s):  
Time Delay ◽  
Delay Line ◽  
Tuning Range ◽  
Rf Mems ◽  
True Time Delay ◽  
True Time ◽  
Line Design

A multi-octave microwave 6-bit true time delay with low amplitude and delay variation in 65 nm CMOS

2021 ◽  
pp. 1-10
Author(s):  
Yakov Gutkin ◽  
Asher Madjar ◽  
Emanuel Cohen
Keyword(s):  
Time Delay ◽  
Insertion Loss ◽  
Impedance Matching ◽  
Least Significant Bit ◽  
Delay Cell ◽  
True Time Delay ◽  
Unit Cells ◽  
True Time ◽  
And Performance ◽  
Low Amplitude

Abstract In this paper, we describe the design, layout, and performance of a 6-bit TTD (true time delay) chip operating over the entire band of 2–18 GHz. The 1.15 mm2 chip is implemented using TSMC foundry 65 nm technology. The least significant bit is 1 ps. The design is based on the concept of all-pass network with some modifications intended to reduce the number of unit cells. Thus, the first three bits are implemented in a single delay cell. A peaking buffer amplifier between bit 4 and bit 5 is used for impedance matching and partial compensation of the insertion loss slope. The rms delay error of the TTD is <1 ps over most of the frequency band and insertion loss is between 2.5 and 6.3 dB for all 64 states.

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