Investigating the Influence of Interconnection Parasitic Inductance on the Performance of SiC Based DC-DC Converters in Hybrid Vehicles

2014 ◽  
Author(s):  
Di Han ◽  
Woongkul Lee ◽  
Jukkrit Noppakunkajorn ◽  
Bulent Sarlioglu
Keyword(s):  
Hybrid Vehicles ◽  
Parasitic Inductance

Hybrid Vehicles

CFA Magazine ◽  
2008 ◽  
Vol 19 (6) ◽  
pp. 26-31
Author(s):  
John Rubino
Keyword(s):  
Hybrid Vehicles

The Impact of Hybrid Vehicles on Street Crossings

2006 ◽  
Vol 38 (2) ◽  
pp. 65-78 ◽  
Author(s):  
William Wiener ◽  
Koorosh Naghshineh ◽  
Brad Salisbury ◽  
Randall Rozema
Keyword(s):  
Hybrid Vehicles ◽  
The Impact

scholarly journals Design and Switching Characteristics of Flip-Chip GaN Half-Bridge Modules Integrated with Drivers

2021 ◽  
Vol 11 (15) ◽  
pp. 7057
Author(s):  
Lin Wang ◽  
Zhe Cheng ◽  
Zhi-Guo Yu ◽  
De-Feng Lin ◽  
Zhe Liu ◽  
...  
Keyword(s):  
Flip Chip ◽  
High Electron Mobility Transistors ◽  
Wire Bonding ◽  
High Electron ◽  
Parasitic Inductance ◽  
Switching Performance ◽  
Turn On ◽  
Electron Mobility Transistors ◽  
Chip Technology ◽  
Switching Characteristics

Half-bridge modules with integrated GaN high electron mobility transistors (HEMTs) and driver dies were designed and fabricated in this research. Our design uses flip-chip technology for fabrication, instead of more generally applied wire bonding, to reduce parasitic inductance in both the driver-gate and drain-source loops. Modules were prepared using both methods and the double-pulse test was applied to evaluate and compare their switching characteristics. The gate voltage (Vgs) waveform of the flip-chip module showed no overshoot during the turn-on period, and a small oscillation during the turn-off period. The probabilities of gate damage and false turn-on were greatly reduced. The inductance in the drain-source loop of the module was measured to be 3.4 nH. The rise and fall times of the drain voltage (Vds) were 12.9 and 5.8 ns, respectively, with an overshoot of only 4.8 V during the turn-off period under Vdc = 100 V. These results indicate that the use of flip-chip technology along with the integration of GaN HEMTs with driver dies can effectively reduce the parasitic inductance and improve the switching performance of GaN half-bridge modules compared to wire bonding.

An improved mini-channel based liquid cooling strategy of prismatic LiFePO4 batteries for electric or hybrid vehicles

2021 ◽  
Vol 35 ◽  
pp. 102301
Author(s):  
K. Monika ◽  
Chanchal Chakraborty ◽  
Sounak Roy ◽  
Srikanta Dinda ◽  
Satyapaul A. Singh ◽  
...  
Keyword(s):  
Hybrid Vehicles ◽  
Liquid Cooling ◽  
Cooling Strategy

scholarly journals Case Study on Fire Resistance of Sandwiches for Means of Transport

Coatings ◽  
2021 ◽  
Vol 11 (2) ◽  
pp. 207
Author(s):  
Pavel Koštial ◽  
Zora Koštialová Jančíková ◽  
Robert Frischer
Keyword(s):  
Fire Resistance ◽  
Fire Protection ◽  
Public Transport ◽  
Hybrid Vehicles ◽  
Safety Requirements ◽  
Different Types ◽  
Aluminum Honeycomb ◽  
Heat Loads

These days there are undeniably unique materials that, however, must also meet demanding safety requirements. In the case of vehicles, these are undoubtedly excellent fire protection characteristics. The aim of the work is to experimentally verify the proposed material compositions for long-term heat loads and the effect of thickness, the number of laminating layers (prepregs) as well as structures with different types of cores (primarily honeycomb made of Nomex paper type T722 of different densities, aluminum honeycomb and PET foam) and composite coating based on a glass-reinforced phenolic matrix. The selected materials are suitable candidates for intelligent sandwich structures, usable especially for interior cladding applications in the industry for the production of means of public transport (e.g., train units, trams, buses, hybrid vehicles).

scholarly journals Parasitic Loop Inductances Reduction in the PCB Layout in GaN-Based Power Converters Using S-Parameters and EM Simulations

Energies ◽  
2021 ◽  
Vol 14 (5) ◽  
pp. 1495
Author(s):  
Loris Pace ◽  
Nadir Idir ◽  
Thierry Duquesne ◽  
Jean-Claude De Jaeger
Keyword(s):  
High Frequency ◽  
Printed Circuit Board ◽  
Power Converters ◽  
Calibration Procedure ◽  
Circuit Board ◽  
Design System ◽  
Switching Speed ◽  
Parasitic Inductance ◽  
Frequency Converters ◽  
S Parameters

Due to the high switching speed of Gallium Nitride (GaN) transistors, parasitic inductances have significant impacts on power losses and electromagnetic interferences (EMI) in GaN-based power converters. Thus, the proper design of high-frequency converters in a simulation tool requires accurate electromagnetic (EM) modeling of the commutation loops. This work proposes an EM modeling of the parasitic inductance of a GaN-based commutation cell on a printed circuit board (PCB) using Advanced Design System (ADS®) software. Two different PCB designs of the commutation loop, lateral (single-sided) and vertical (double-sided) are characterized in terms of parasitic inductance contribution. An experimental approach based on S-parameters, the Cold FET technique and a specific calibration procedure is developed to obtain reference values for comparison with the proposed models. First, lateral and vertical PCB loop inductances are extracted. Then, the whole commutation loop inductances including the packaging of the GaN transistors are determined by developing an EM model of the device’s internal parasitic. The switching waveforms of the GaN transistors in a 1 MHz DC/DC converter are given for the different commutation loop designs. Finally, a discussion is proposed on the presented results and the development of advanced tools for high-frequency GaN-based power electronics design.

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