A RDT-based interconnection network for scalable network-on-chip designs

2005 ◽  
Author(s):  
Yang Yu ◽  
Mei Yang ◽  
Yulu Yang ◽  
Yingtao Jiang
Keyword(s):  
Interconnection Network ◽  
Network On Chip ◽  
On Chip ◽  
Scalable Network

Highly scalable network on chip for reconfigurable systems

2004 ◽  
Author(s):  
T.A. Bartic ◽  
J.-Y. Mignolet ◽  
V. Nollet ◽  
T. Marescaux ◽  
D. Verkest ◽  
...  
Keyword(s):  
Network On Chip ◽  
Reconfigurable Systems ◽  
On Chip ◽  
Scalable Network

A Scalable Network-on-Chip Microprocessor With 2.5D Integrated Memory and Accelerator

2017 ◽  
Vol 64 (6) ◽  
pp. 1432-1443 ◽  
Author(s):  
Sai Manoj P.D. ◽  
Zhiyi Yu ◽  
Hao Yu ◽  
Jie Lin ◽  
Shikai Zhu ◽  
...  
Keyword(s):  
Network On Chip ◽  
On Chip ◽  
Scalable Network

Architecture and Network-on-Chip Implementation of a New Hierarchical Interconnection Network

2014 ◽  
Vol 24 (02) ◽  
pp. 1540006 ◽  
Author(s):  
M. M. Hafizur Rahman ◽  
Rizal Mohd Nor ◽  
Tengku Mohd Bin Tengku Sembok ◽  
M. A. H. Akhand
Keyword(s):  
Mesh Networks ◽  
Fault Tolerant ◽  
Interconnection Network ◽  
Average Distance ◽  
Small Diameter ◽  
Network On Chip ◽  
Mesh Network ◽  
Minimal Distance ◽  
Bisection Width ◽  
On Chip

A Midimew-connected Mesh Network (MMN) is a minimal distance mesh with wrap-around links network of multiple basic modules (BMs), in which the BMs are 2D-mesh networks that are hierarchically interconnected for higher-level networks. In this paper, we present the architecture of the MMN, addressing of node, routing of message, and evaluate the static network performance of MMN, TESH, mesh and torus networks. In addition, we propose the network-on-chip (NoC) implementation of MMN. With innovative combination of diagonal and hierarchical structure, the MMN possesses several attractive features, including constant degree, small diameter, low cost, small average distance, moderate bisection width and high fault tolerant performance than that of other conventional and hierarchical interconnection networks. The simple architecture of MMN is also highly suitable for NoC implementation. To implement all the links of level-3 MMN, only four layers are needed which is feasible with current and future VLSI technologies.

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