4GHz+ low-latency fixed-point and binary floating-point execution units for the POWER6 processor

2006 ◽  
Author(s):  
B. Curran ◽  
B. McCredie ◽  
L. Sigal ◽  
E. Schwarz ◽  
B. Fleischer ◽  
...  
Keyword(s):  
Fixed Point ◽  
Floating Point ◽  
Low Latency

scholarly journals A Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier on a Virtex-5 FPGA

2010 ◽  
Vol 2010 ◽  
pp. 1-13 ◽  
Author(s):  
Malte Baesler ◽  
Sven-Ole Voigt ◽  
Thomas Teufel
Keyword(s):  
Fixed Point ◽  
Scalar Product ◽  
Floating Point ◽  
Low Latency ◽  
Partial Product ◽  
Rounding Error ◽  
Data Format ◽  
Product Generation

Decimal Floating Point operations are important for applications that cannot tolerate errors from conversions between binary and decimal formats, for instance, commercial, financial, and insurance applications. In this paper, we present a parallel decimal fixed-point multiplier designed to exploit the features of Virtex-5 FPGAs. Our multiplier is based on BCD recoding schemes, fast partial product generation, and a BCD-4221 carry save adder reduction tree. Pipeline stages can be added to target low latency. Furthermore, we extend the multiplier with an accurate scalar product unit for IEEE 754-2008decimal64data format in order to provide an important operation with least possible rounding error. Compared to a previously published work, in this paper, we improve the architecture of the accurate scalar product unit and migrate to Virtex-5 FPGAs. This decreases the fixed-point multiplier's latency by a factor of two and the accurate scalar product unit's latency even by a factor of five.

IEEE-754 Half-Precision Floating-Point Low-Latency Reciprocal Square Root IP-Core

2018 ◽  
Author(s):  
Cuauhtemoc R. Aguilera-Galicia ◽  
Omar Longoria-Gandara ◽  
Oscar A. Guzman-Ramos ◽  
Luis Pizano-Escalante ◽  
Javier Vazouez-Castillo
Keyword(s):  
Floating Point ◽  
Low Latency ◽  
Square Root ◽  
Ip Core
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