A Watermarking System for IP Protection by Buffer Insertion Technique

2006 ◽  
Author(s):  
Guangyu Sun ◽  
Zhiqiang Gao ◽  
Yi Xu
Keyword(s):  
Buffer Insertion ◽  
Insertion Technique ◽  
Ip Protection

scholarly journals On-chip interconnects modeling and timing driven buffer insertion

2021 ◽  
Author(s):  
Alaa R. Abdullah
Keyword(s):  
Closed Form ◽  
Performance Modeling ◽  
Vlsi Design ◽  
Electrical Circuit ◽  
Equivalent Electrical Circuit ◽  
Buffer Insertion ◽  
Insertion Technique ◽  
Rc Circuit ◽  
On Chip ◽  
Transition Times

With the increasing effect of on-chip interconnects on nowadays [sic] VLSI design performance, modeling of interconnects becomes a necessity. GAM, TPN, and AWE are well known methods that are used to map an interconnect to an equivalent electrical circuit. In this thesis, a general approach that considers z-parameters is developed witch allows the generation of equivalent RC, RLC, and RLCG circuits for both T and ∏ configurations. The performance of these generated circuits is compared to H-spice simulations by measuring the effect of interconnects on the transition times and delays under different conditions such as input transition times, interconnect lengths and capacitive loads. As a result, the a-configuration of AWE method reveals consistently an acceptable performance which makes it a good candidate to be utilized for buffer insertion.Buffer insertion is a popular technique used to reduce the delay of a long interconnect by segmenting it and inserting buffers among these segments. Therefore, the performance of this technique depends strongly on the accuracy of the considered interconnect model. However, using a model such as the RLCG of ∏ configuration which is derived from using the AWE method is not practical due to the complexity accompanied by such model which makes the derivation of closed-form expressions very complicated. To overcome this dilemma, the selected configuration has been mapped to a simple equivalent RC circuit. As a consequence, a new RC representation of on-chip interconnects is developed. Moreover, depending on the developed RC model, the proposed buffer insertion technique shows superiority over previously published works.

scholarly journals On-chip interconnects modeling and timing driven buffer insertion

2021 ◽  
Author(s):  
Alaa R. Abdullah
Keyword(s):  
Closed Form ◽  
Performance Modeling ◽  
Vlsi Design ◽  
Electrical Circuit ◽  
Equivalent Electrical Circuit ◽  
Buffer Insertion ◽  
Insertion Technique ◽  
Rc Circuit ◽  
On Chip ◽  
Transition Times

With the increasing effect of on-chip interconnects on nowadays [sic] VLSI design performance, modeling of interconnects becomes a necessity. GAM, TPN, and AWE are well known methods that are used to map an interconnect to an equivalent electrical circuit. In this thesis, a general approach that considers z-parameters is developed witch allows the generation of equivalent RC, RLC, and RLCG circuits for both T and ∏ configurations. The performance of these generated circuits is compared to H-spice simulations by measuring the effect of interconnects on the transition times and delays under different conditions such as input transition times, interconnect lengths and capacitive loads. As a result, the a-configuration of AWE method reveals consistently an acceptable performance which makes it a good candidate to be utilized for buffer insertion.Buffer insertion is a popular technique used to reduce the delay of a long interconnect by segmenting it and inserting buffers among these segments. Therefore, the performance of this technique depends strongly on the accuracy of the considered interconnect model. However, using a model such as the RLCG of ∏ configuration which is derived from using the AWE method is not practical due to the complexity accompanied by such model which makes the derivation of closed-form expressions very complicated. To overcome this dilemma, the selected configuration has been mapped to a simple equivalent RC circuit. As a consequence, a new RC representation of on-chip interconnects is developed. Moreover, depending on the developed RC model, the proposed buffer insertion technique shows superiority over previously published works.

A Silicon Debugging Methodology on Customer Prototype for Wafer Foundries

2012 ◽  
Author(s):  
Mai Zhihong ◽  
Ng Tsu Hau ◽  
Dawood M. Khalid ◽  
Tan Pik Kee ◽  
Jeffrey Lam
Keyword(s):  
Case Studies ◽  
Semiconductor Industry ◽  
Full Information ◽  
Limited Information ◽  
Ip Protection ◽  
First Case ◽  
Silicon Debugging ◽  
Failure Location ◽  
Device Chip ◽  
Latch Up

Abstract IP protection is of major importance for a semiconductor company and only limited information is made available for device debugging for the product outsourced to a foundry. In order to position ourselves better in the ever competitive semiconductor industry, with the consideration of IP protection, we have to provide the customers with the Si debugging capability and device/chip verification services in foundry. This paper explores the Si debugging methodology and technique in a foundry. Two case studies are presented and discussed. The first case illustrates the isolation of the failure location by InGaAs microscopy, upon which the failure was identified to be caused by a latch-up issue. In the second case, due to confidentiality considerations from the customer, full information could not be provided to the foundry for silicon debugging. The paper illustrates the ability to effectively debug a failure despite being constrained by limited information from the customer.

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