Memory Hierarchy Optimization for Large Tridiagonal System Solvers on GPU

2012 ◽  
Author(s):  
Juli'n Lamas-Rodriguez ◽  
Francisco Arguello ◽  
Dora B. Heras ◽  
Montserrat Boo
Keyword(s):  
Memory Hierarchy ◽  
Memory Hierarchy Optimization

scholarly journals Specific read only data management for memory hierarchy optimization

2015 ◽  
Vol 11 (4) ◽  
pp. 55-60
Author(s):  
Gregory Vaumourin ◽  
Dombek Thomas ◽  
Guerre Alexandre ◽  
Denis Barthou
Keyword(s):  
Data Management ◽  
Memory Hierarchy ◽  
Memory Hierarchy Optimization

Bit-Width Constrained Memory Hierarchy Optimization for Real-Time Video Systems

2007 ◽  
Vol 26 (4) ◽  
pp. 781-800 ◽  
Author(s):  
Benny Thornberg ◽  
Martin Palkovic ◽  
Qubo Hu ◽  
Leif Olsson ◽  
Per Gunnar Kjeldsberg ◽  
...  
Keyword(s):  
Real Time ◽  
Memory Hierarchy ◽  
Video Systems ◽  
Memory Hierarchy Optimization

scholarly journals MILC Code Performance on High End CPU and GPU Supercomputer Clusters

2018 ◽  
Vol 175 ◽  
pp. 02009
Author(s):  
Carleton DeTar ◽  
Steven Gottlieb ◽  
Ruizi Li ◽  
Doug Toussaint
Keyword(s):  
Conjugate Gradient ◽  
Memory Hierarchy ◽  
Xeon Phi ◽  
Intel Xeon Phi ◽  
Code Performance ◽  
Recent Developments ◽  
Knights Landing ◽  
Many Core ◽  
Intel Xeon

With recent developments in parallel supercomputing architecture, many core, multi-core, and GPU processors are now commonplace, resulting in more levels of parallelism, memory hierarchy, and programming complexity. It has been necessary to adapt the MILC code to these new processors starting with NVIDIA GPUs, and more recently, the Intel Xeon Phi processors. We report on our efforts to port and optimize our code for the Intel Knights Landing architecture. We consider performance of the MILC code with MPI and OpenMP, and optimizations with QOPQDP and QPhiX. For the latter approach, we concentrate on the staggered conjugate gradient and gauge force. We also consider performance on recent NVIDIA GPUs using the QUDA library.

Cache and Memory Hierarchy Design

1995 ◽  
Vol 23 (3) ◽  
pp. 28
Author(s):  
Daniel Tabak
Keyword(s):  
Memory Hierarchy

Novel memory hierarchy with e-STT-MRAM for near-future applications

2017 ◽  
Author(s):  
Shinobu Fujita ◽  
Hiroki Noguchi ◽  
Kazutaka Ikegami ◽  
Susumu Takeda ◽  
Kumiko Nomura ◽  
...  
Keyword(s):  
Memory Hierarchy ◽  
Near Future

EXPLOITING THE MEMORY HIERARCHY OF MULTICORE SYSTEMS FOR PARALLEL TRIANGULATION REFINEMENT

2012 ◽  
Vol 22 (03) ◽  
pp. 1250007 ◽  
Author(s):  
PEDRO RODRÍGUEZ ◽  
MARÍA CECILIA RIVARA ◽  
ISAAC D. SCHERSON
Keyword(s):  
Parallel Implementation ◽  
Memory Hierarchy ◽  
Random Selection ◽  
Multicore Systems ◽  
Algorithm Performance ◽  
Bisection Algorithm ◽  
Improve Algorithm ◽  
Triangulation Refinement ◽  
Selection Of

A novel parallelization of the Lepp-bisection algorithm for triangulation refinement on multicore systems is presented. Randomization and wise use of the memory hierarchy are shown to highly improve algorithm performance. Given a list of selected triangles to be refined, random selection of candidates together with pre-fetching of Lepp-submeshes lead to a scalable and efficient multi-core parallel implementation. The quality of the refinement is shown to be preserved.

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