Logic for static hazard detection of multiple-valued logic circuits with TSUM, MIN, and Literals

2003 ◽  
Author(s):  
N. Tkagi ◽  
K. Nakashima
Keyword(s):  
Logic Circuits ◽  
Multiple Valued Logic ◽  
Hazard Detection

scholarly journals Quaternary regenerative CMOS logic circuits with high-impedance output state

2005 ◽  
Vol 18 (3) ◽  
pp. 505-514
Author(s):  
Dusanka Bundalo ◽  
Branimir Ðordjevic ◽  
Zlatko Bundalo
Keyword(s):  
Computer Simulation ◽  
Computer Simulations ◽  
Delay Time ◽  
Propagation Delay ◽  
Logic Circuits ◽  
Output State ◽  
High Impedance ◽  
Multiple Valued Logic ◽  
Propagation Delay Time ◽  
Simulation Results

Principles and possibilities of synthesis and design of quaternary multiple valued regenerative CMOS logic circuits with high-impedance output state are de- scribed and proposed in the paper. Two principles of synthesis and implementation of CMOS regenerative quaternary multiple-valued logic circuits with high-impedance output state are proposed and described: the simple circuits with smaller number of transistors, and the buffer/driver circuits with decreased propagation delay time. The schemes of such logic circuits are given and analyzed by computer simulations. Some of computer simulation results confirming descriptions and conclusions are also given in the paper.

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