Design of Rate-Compatible Irregular LDPC Codes for Incremental Redundancy Hybrid ARQ Systems

2006 IEEE International Symposium on Information Theory ◽

10.1109/isit.2006.261962 ◽

2006 ◽

Cited By ~ 30

Author(s):

Jaehong Kim ◽

Woonhaing Hur ◽

Aditya Ramamoorthy ◽

Steven McLaughlin

Keyword(s):

Ldpc Codes ◽

Hybrid Arq ◽

Incremental Redundancy ◽

Irregular Ldpc Codes

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A new reliability-based incremental redundancy hybrid ARQ scheme using LDPC codes

2015 IEEE 14th Canadian Workshop on Information Theory (CWIT) ◽

10.1109/cwit.2015.7255170 ◽

2015 ◽

Cited By ~ 2

Author(s):

Hamid Saber ◽

Ian Marsland

Keyword(s):

Ldpc Codes ◽

Hybrid Arq ◽

Incremental Redundancy

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Incremental Redundancy Hybrid ARQ (IR-HARQ) Scheme Using Block LDPC Codes

The Journal of Korean Institute of Communications and Information Sciences ◽

10.7840/kics.2013.38a.8.662 ◽

2013 ◽

Vol 38A (8) ◽

pp. 662-668 ◽

Cited By ~ 1

Author(s):

Dong Ho Kim ◽

Ye Hoon Lee

Keyword(s):

Ldpc Codes ◽

Hybrid Arq ◽

Incremental Redundancy

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On the Performance of Incremental Redundancy Hybrid ARQ Schemes with Rate Compatible LDPC Codes

2006 International Conference on Communications, Circuits and Systems ◽

10.1109/icccas.2006.284758 ◽

2006 ◽

Cited By ~ 2

Author(s):

Hong Wen ◽

Liang Zhou ◽

Chusheng Fu

Keyword(s):

Ldpc Codes ◽

Hybrid Arq ◽

Incremental Redundancy ◽

Arq Schemes

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Design and Construction of Irregular LDPC Codes for Channels with Synchronization Errors: New Aspect of Degree Profiles

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.2020eap1004 ◽

2020 ◽

Vol E103.A (10) ◽

pp. 1237-1247

Author(s):

Ryo SHIBATA ◽

Gou HOSOYA ◽

Hiroyuki YASHIMA

Keyword(s):

Ldpc Codes ◽

Synchronization Errors ◽

Irregular Ldpc Codes ◽

Design And Construction

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Performance of hybrid-ARQ with incremental redundancy over relay channels

2012 IEEE Globecom Workshops ◽

10.1109/glocomw.2012.6477555 ◽

2012 ◽

Cited By ~ 6

Author(s):

Ali Chelli ◽

Mohamed-Slim Alouini

Keyword(s):

Relay Channels ◽

Hybrid Arq ◽

Incremental Redundancy

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Optimal rate for irregular LDPC codes in binary erasure channel

2011 IEEE Information Theory Workshop ◽

10.1109/itw.2011.6089360 ◽

2011 ◽

Cited By ~ 5

Author(s):

H. Tavakoli ◽

M. Ahmadian Attari ◽

M. Reza Peyghami

Keyword(s):

Ldpc Codes ◽

Optimal Rate ◽

Irregular Ldpc Codes ◽

Erasure Channel ◽

Binary Erasure Channel

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Performance analysis of hybrid-ARQ systems with LDPC codes

2011 IEEE 19th Signal Processing and Communications Applications Conference (SIU) ◽

10.1109/siu.2011.5929799 ◽

2011 ◽

Author(s):

Onural Cimenler ◽

Mehmet Safak

Keyword(s):

Performance Analysis ◽

Ldpc Codes ◽

Hybrid Arq

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Design of irregular LDPC codes for BIAWGN channels with SNR mismatch

IEEE Transactions on Communications ◽

10.1109/tcomm.2009.0901.060118 ◽

2009 ◽

Vol 57 (1) ◽

pp. 6-11 ◽

Cited By ~ 12

Author(s):

Hamid Saeedi ◽

Amir H. Banihashemi

Keyword(s):

Ldpc Codes ◽

Irregular Ldpc Codes

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FPGA Implementation of Decoder Architectures for High Throughput Irregular LDPC Codes

Indian Journal of Science and Technology ◽

10.17485/ijst/2016/v9i48/97269 ◽

2016 ◽

Vol 9 (48) ◽

Cited By ~ 1

Author(s):

Sandeep Kakde ◽

Atish Khobragade ◽

M. D. Ekbal Husain

Keyword(s):

High Throughput ◽

Ldpc Codes ◽

Fpga Implementation ◽

Irregular Ldpc Codes

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Design of structured irregular LDPC codes

2008 IEEE Region 8 International Conference on Computational Technologies in Electrical and Electronics Engineering ◽

10.1109/sibircon.2008.4602580 ◽

2008 ◽

Cited By ~ 2

Author(s):

Peter Trifonov

Keyword(s):

Ldpc Codes ◽

Irregular Ldpc Codes

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