A Novel Low Power Noise Tolerant High Performance Dynamic Feed through Logic Design Technique

2011 ◽  
Author(s):  
Manisha Pattanaik ◽  
Shashank Parashar ◽  
Chaudhry Indra Kumar ◽  
Akanksha Chouhan ◽  
Vikas Mahor
Keyword(s):  
Low Power ◽  
High Performance ◽  
Logic Design ◽  
Design Technique ◽  
Power Noise ◽  
Noise Tolerant

Skewed CMOS: noise-tolerant high-performance low-power static circuit family

2002 ◽  
Vol 10 (4) ◽  
pp. 469-476 ◽  
Author(s):  
A. Solomatnikov ◽  
D. Somasekhar ◽  
N. Sirisantana ◽  
K. Roy
Keyword(s):  
Low Power ◽  
High Performance ◽  
Noise Tolerant ◽  
Circuit Family

Nanoscale: Low Power, Noise Tolerant Wide Fan-In Domino FinFET OR Logic

2018 ◽  
Vol 13 (4) ◽  
pp. 562-571
Author(s):  
Ajay Kumar Dadoria ◽  
Kavita Khare ◽  
Tarun K. Gupta ◽  
Rajendra Prasad Singh
Keyword(s):  
Low Power ◽  
Power Noise ◽  
Noise Tolerant

Evolutionary Approach of Adiabatic Logic Design on Low Power Solution �A Robust Survey

2012 ◽  
Vol 1 (2) ◽  
pp. 36-49
Author(s):  
A. Kishore Kumar ◽  
D. Somasundareswari ◽  
V. Duraisamy ◽  
T. Shunbaga Pradeepa
Keyword(s):  
Low Power ◽  
Evolutionary Approach ◽  
Logic Design ◽  
Adiabatic Logic

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

High-Performance and Low-Power Full Color Reflective LCD for New Applications

2019 ◽  
pp. 1411
Author(s):  
Hiroyuki Hakoi ◽  
Ming Ni ◽  
Junichi Hashimoto ◽  
Takashi Sato ◽  
Shinji Shimada ◽  
...  
Keyword(s):  
Low Power ◽  
High Performance ◽  
Full Color ◽  
New Applications
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