Instruction Scheduling on Variable Latency Functional Units of VLIW Processors

2011 International Symposium on Electronic System Design ◽

10.1109/ised.2011.50 ◽

2011 ◽

Cited By ~ 2

Author(s):

Nayan V. Mujadiya

Keyword(s):

Instruction Scheduling ◽

Vliw Processors ◽

Variable Latency ◽

Functional Units

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An efficient heuristic for instruction scheduling on clustered vliw processors

Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems - CASES '11 ◽

10.1145/2038698.2038707 ◽

2011 ◽

Cited By ~ 5

Author(s):

Xuemeng Zhang ◽

Hui Wu ◽

Jingling Xue

Keyword(s):

Instruction Scheduling ◽

Vliw Processors

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Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units

Lecture Notes in Computer Science - Computer Systems: Architectures, Modeling, and Simulation ◽

10.1007/978-3-540-27776-7_10 ◽

2004 ◽

pp. 88-97

Author(s):

Miquel Pericàs ◽

Eduard Ayguadé ◽

Javier Zalamea ◽

Josep Llosa ◽

Mateo Valero

Keyword(s):

Vliw Processors ◽

Functional Units ◽

Power Evaluation

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Instruction scheduling for VLIW processors under variation scenario

2009 International Symposium on Systems, Architectures, Modeling, and Simulation ◽

10.1109/icsamos.2009.5289239 ◽

2009 ◽

Cited By ~ 1

Author(s):

Nayan V. Mujadiya

Keyword(s):

Instruction Scheduling ◽

Vliw Processors

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Checkpoint-aware instruction scheduling for nonvolatile processor with multiple functional units

The 20th Asia and South Pacific Design Automation Conference ◽

10.1109/aspdac.2015.7059024 ◽

2015 ◽

Cited By ~ 1

Author(s):

Mimi Xie ◽

Chen Pan ◽

Jingtong Hu ◽

Chengmo Yang ◽

Yiran Chen

Keyword(s):

Instruction Scheduling ◽

Functional Units

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Functional units with conditional input/output behavior in VLIW processors

Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001 ◽

10.1109/date.2001.915171 ◽

2002 ◽

Author(s):

M.J.G. Bekooij ◽

L.J.M. Engels ◽

A. van der Werf ◽

G. Busa

Keyword(s):

Input Output ◽

Vliw Processors ◽

Functional Units ◽

Output Behavior

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Instruction scheduling with k-successor tree for clustered VLIW processors

Design Automation for Embedded Systems ◽

10.1007/s10617-012-9103-0 ◽

2013 ◽

Vol 17 (2) ◽

pp. 439-458 ◽

Cited By ~ 1

Author(s):

Xuemeng Zhang ◽

Hui Wu ◽

Jingling Xue

Keyword(s):

Instruction Scheduling ◽

Vliw Processors

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Instruction scheduling heuristic for an efficient FFT in VLIW processors with balanced resource usage

EURASIP Journal on Advances in Signal Processing ◽

10.1186/s13634-016-0336-0 ◽

2016 ◽

Vol 2016 (1) ◽

Cited By ~ 2

Author(s):

Mounir Bahtat ◽

Said Belkouch ◽

Philippe Elleaume ◽

Philippe Le Gall

Keyword(s):

Instruction Scheduling ◽

Resource Usage ◽

Vliw Processors ◽

Scheduling Heuristic

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Certified and efficient instruction scheduling: application to interlocked VLIW processors

Proceedings of the ACM on Programming Languages ◽

10.1145/3428197 ◽

2020 ◽

Vol 4 (OOPSLA) ◽

pp. 1-29

Author(s):

Cyril Six ◽

Sylvain Boulmé ◽

David Monniaux

Keyword(s):

Instruction Scheduling ◽

Vliw Processors

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Instruction Scheduling for Clustered VLIW Processors

Code Optimization Techniques for Embedded Processors ◽

10.1007/978-1-4757-3169-9_4 ◽

2000 ◽

pp. 81-100 ◽

Cited By ~ 2

Author(s):

Rainer Leupers

Keyword(s):

Instruction Scheduling ◽

Vliw Processors

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Aligned Scheduling: Cache-Efficient Instruction Scheduling for VLIW Processors

Languages and Compilers for Parallel Computing - Lecture Notes in Computer Science ◽

10.1007/978-3-319-09967-5_16 ◽

2014 ◽

pp. 275-291

Author(s):

Vasileios Porpodas ◽

Marcelo Cintra

Keyword(s):

Instruction Scheduling ◽

Vliw Processors ◽

Cache Efficient

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