A low-power second-order double-sampling delta-sigma modulator for audio applications

2014 ◽  
Author(s):  
Junbo Shim ◽  
Seong-Kwan Hong ◽  
Oh-Kyong Kwon
Keyword(s):  
Low Power ◽  
Second Order ◽  
Double Sampling ◽  
Delta Sigma Modulator ◽  
Delta Sigma

scholarly journals A Low-Power Opamp-Less Second-Order Delta-Sigma Modulator for Bioelectrical Signals in 0.18 µm CMOS

Sensors ◽  
2021 ◽  
Vol 21 (19) ◽  
pp. 6456
Author(s):  
Fernando Cardes ◽  
Nikhita Baladari ◽  
Jihyun Lee ◽  
Andreas Hierlemann
Keyword(s):  
Low Power ◽  
Low Frequency ◽  
Cmos Technology ◽  
Low Noise ◽  
Second Order ◽  
Frequency Noise ◽  
Voltage Controlled Oscillator ◽  
Noise Shaping ◽  
Delta Sigma Modulator ◽  
Delta Sigma

This article reports on a compact and low-power CMOS readout circuit for bioelectrical signals based on a second-order delta-sigma modulator. The converter uses a voltage-controlled, oscillator-based quantizer, achieving second-order noise shaping with a single opamp-less integrator and minimal analog circuitry. A prototype has been implemented using 0.18 μm CMOS technology and includes two different variants of the same modulator topology. The main modulator has been optimized for low-noise, neural-action-potential detection in the 300 Hz–6 kHz band, with an input-referred noise of 5.0 μVrms, and occupies an area of 0.0045 mm2. An alternative configuration features a larger input stage to reduce low-frequency noise, achieving 8.7 μVrms in the 1 Hz–10 kHz band, and occupies an area of 0.006 mm2. The modulator is powered at 1.8 V with an estimated power consumption of 3.5 μW.

A Wideband Continuous Time Quadrature Delta Sigma Modulator Based on a Real DSM for Low Power WLAN Receiver

2017 ◽  
Vol 27 (03) ◽  
pp. 1850044 ◽  
Author(s):  
Alireza Shamsi ◽  
Esmaeil Najafi Aghdam
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Continuous Time ◽  
Signal To Noise Ratio ◽  
System Level ◽  
Complex Coefficient ◽  
Loop Filter ◽  
Delta Sigma Modulator ◽  
Delta Sigma ◽  
Excess Loop Delay

Power consumption and bandwidth are two of the most important parameters in design of low power wideband modulators as power consumption is growing with the increase in bandwidth. In this study, a multi bit wideband low-power continuous time feed forward quadrature delta sigma modulator (CT-FF-QDSM) is designed for WLAN receiver applications by eliminating adders from modulator structure. In this method, a real modulator is designed and its excess loop delay (ELD) is compensated, then, it is converted into a quadrature structure by applying the complex coefficient to loop filter. Complex coefficients are extracted by the aid of a genetic algorithm to further improve signal to noise ratio (SNR) for bandwidth. One of the disadvantages of CT-FF-QDSM is the adders of loop filters which are power hungry and reduce the effective loop gain. Therefore, the adders have been eliminated while the transfer function is intact in the final modulator. The system level SNR of the proposed modulator is 62.53[Formula: see text]dB using OSR of 12. The circuit is implemented in CMOSTSMC180nm technology. The circuit levels SNR and power consumption are 54[Formula: see text]dB and 13.5[Formula: see text]mW, respectively. Figure of Merit (FOM) obtained from the proposed modulator is about 0.824 (pj/conv) which is improved (by more than 40%) compared to the previous designs.

A 16-bit low-power double-sampled delta sigma modulator for audio applications

2015 ◽  
Author(s):  
Yongsheng Wang ◽  
Hongying Wang ◽  
Fengchang Lai ◽  
Bei Cao ◽  
Yang Liu ◽  
...  
Keyword(s):  
Low Power ◽  
Delta Sigma Modulator ◽  
Delta Sigma

An Ultra-Low-Power, 16 Bits CT Delta-Sigma Modulator Using 4-Bit Asynchronous SAR Quantizer for Medical Applications

2019 ◽  
Vol 29 (04) ◽  
pp. 2050056
Author(s):  
Sahel Javahernia ◽  
Esmaeil Najafi Aghdam ◽  
Pooya Torkzadeh
Keyword(s):  
Low Power ◽  
Cmos Technology ◽  
Digital To Analog Converter ◽  
Ultra Low Power ◽  
Feed Forward ◽  
Delta Sigma Modulator ◽  
Delta Sigma ◽  
Summing Amplifier ◽  
Capacitor Structure ◽  
Asynchronous Sar

In this paper, a low-power second-order feed-forward capacitor-structure continuous-time [Formula: see text] modulator with a 4-bit asynchronous successive approximation register (SAR) quantizer is presented. Through the utilization capacitor structure in the proposed modulator, first, the summation node of the integrators’ outputs and the feed-forward signals is implemented within the second integrator to reduce power consumption by eliminating an active summing amplifier. Second, the proposed architecture can compensate for the quantizer delay without using any excess inner digital to analog converter (DAC). In this design, the modulator applies two different low-power operational amplifiers. These advantages cause the modulator to consume very low power and achieve a favorable figure of merit (FOM) value. In fact, in this paper, the combination of the previously reported methods and designs and doing required reforms has led to a new design with better performance, especially in power reduction. The designed modulator which is simulated using 0.18[Formula: see text][Formula: see text]m CMOS technology achieves 95.98[Formula: see text]dB peak signal-to-noise and distortion (SNDR) for 10[Formula: see text]KHz signal bandwidth and dissipates 44[Formula: see text][Formula: see text]w while its FOM is obtained about 43 fJ/conv.-step.

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