A low-leakage parallel CRC generator for ultra-low power applications

2011 ◽  
Author(s):  
Louis P. Alarcon ◽  
Tsung-Te Liu ◽  
Jan M. Rabaey
Keyword(s):  
Low Power ◽  
Ultra Low Power ◽  
Low Leakage

New Low-leakage Flip-flops with Power-gating Scheme for Ultra-low Power Systems

2011 ◽  
Vol 10 (11) ◽  
pp. 2161-2167 ◽  
Author(s):  
Jianping Hu ◽  
Xiaoying Yu ◽  
Jindan Chen
Keyword(s):  
Power Systems ◽  
Low Power ◽  
Power Gating ◽  
Ultra Low Power ◽  
Low Leakage ◽  
Gating Scheme

scholarly journals High Vt-low Leakage FDSOI Device for Ultra-low Power Operation

2016 ◽  
Vol 9 (33) ◽  
Author(s):  
Manisha Guduri ◽  
Amit Krishna Dwivedi ◽  
Aminul Islam
Keyword(s):  
Low Power ◽  
Ultra Low Power ◽  
Low Leakage ◽  
Power Operation

Low Leakage Highly Stable Robust Ultra Low Power 8T SRAM Cell

2019 ◽  
pp. 643-654 ◽  
Author(s):  
Neha Gupta ◽  
Tanisha Gupta ◽  
Sajid Khan ◽  
Abhinav Vishwakarma ◽  
Santosh Kumar Vishvakarma
Keyword(s):  
Low Power ◽  
Ultra Low Power ◽  
Low Leakage ◽  
Sram Cell

Low Leakage SOI CMOS Static Memory Cell With Ultra-Low Power Diode

2007 ◽  
Vol 42 (3) ◽  
pp. 689-702 ◽  
Author(s):  
David Levacq ◽  
Vincent Dessard ◽  
Denis Flandre
Keyword(s):  
Low Power ◽  
Memory Cell ◽  
Ultra Low Power ◽  
Low Leakage ◽  
Power Diode ◽  
Soi Cmos

scholarly journals TI Low-Leakage130nm Digital Process with Nonvolatile FRAM for Ultra-Low-Power Medical Electronics

2008 ◽  
Vol 2 (2) ◽  
Author(s):  
A. Robert Landers ◽  
B. Jerry Elkind ◽  
C. Rajni Aggarwal
Keyword(s):  
Low Power ◽  
Medical Devices ◽  
Active Power ◽  
Ultra Low Power ◽  
Low Leakage ◽  
Low Duty Cycle ◽  
Static Power ◽  
And Performance ◽  
On Chip ◽  
Medical Design

Both external and implantable devices are becoming more sophisticated and are requiring more on-chip memory to store data from biological sensors. To deal with this complexity, chip designs are moving toward smaller process geometries, which provide added functionality, reduced size, or both, often along with a reduction in dynamic power. However, leakage power begins to increase significantly at the 130nm node if steps are not taken to mitigate the increased transistor leakage. Lower operating voltages and careful transistor design can offset some of this increase. These very changes, however, make it difficult to design a dense, stable low-power SRAM. Nonvolatile memories like FRAM (F-RAM) avoid these difficulties and save power by simply turning off the memory when not in use. This is particularly valuable since many medical devices have very low duty cycle. FRAM provides the added benefit of providing SRAM-like active power, unlike competing nonvolatile technologies. To meet the challenging power requirements of medical devices, a new ultra-low-power 130nm process has been developed. The new process includes a very-high-density, SER-resistant, nonvolatile FRAM and an ultra-low-leakage transistor, coupled with a library that is optimized for low-power operation. This paper compares the power, area and performance of competing process technologies for a typical implantable medical design and highlights the advantages that FRAM provides in low static power through a transparent power-down capability and in low SRAM-like active power.

scholarly journals Low Leakage Current Symmetrical Dual-k 7 nm Trigate Bulk Underlap FinFET for Ultra Low Power Applications

IEEE Access ◽  
2019 ◽  
Vol 7 ◽  
pp. 17256-17262 ◽  
Author(s):  
Mahmoud S. Badran ◽  
Hanady Hussein Issa ◽  
Saleh M. Eisa ◽  
Hani Fikry Ragai
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
Ultra Low Power ◽  
Low Leakage ◽  
Low Leakage Current
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