Phase locked loop robustness improvement using non integer order loop filter

2006 ◽  
Author(s):  
V. Lagareste ◽  
F. Badets ◽  
P. Melchior ◽  
J.B. Begueret ◽  
Y. Deval ◽  
...  
Keyword(s):  
Phase Locked Loop ◽  
Loop Filter ◽  
Integer Order

scholarly journals A phase-locked loop using ESO-based loop filter for grid-connected converter: performance analysis

2021 ◽  
Author(s):  
Baoling Guo ◽  
Seddik Bacha ◽  
Mazen Alamir ◽  
Julien Pouget
Keyword(s):  
Performance Analysis ◽  
Frequency Domain ◽  
Low Frequency ◽  
Experimental Tests ◽  
Frequency Measurement ◽  
Phase Locked Loop ◽  
Frequency Domain Analysis ◽  
Loop Filter ◽  
Control Stability ◽  
Unbalanced Grid

AbstractAn extended state observer (ESO)-based loop filter is designed for the phase-locked loop (PLL) involved in a disturbed grid-connected converter (GcC). This ESO-based design enhances the performances and robustness of the PLL, and, therefore, improves control performances of the disturbed GcCs. Besides, the ESO-based LF can be applied to PLLs with extra filters for abnormal grid conditions. The unbalanced grid is particularly taken into account for the performance analysis. A tuning approach based on the well-designed PI controller is discussed, which results in a fair comparison with conventional PI-type PLLs. The frequency domain properties are quantitatively analysed with respect to the control stability and the noises rejection. The frequency domain analysis and simulation results suggest that the performances of the generated ESO-based controllers are comparable to those of the PI control at low frequency, while have better ability to attenuate high-frequency measurement noises. The phase margin decreases slightly, but remains acceptable. Finally, experimental tests are conducted with a hybrid power hardware-in-the-loop benchmark, in which balanced/unbalanced cases are both explored. The obtained results prove the effectiveness of ESO-based PLLs when applied to the disturbed GcC.

Design and performance study of phase-locked loop using fractional-order loop filter

2014 ◽  
Vol 43 (6) ◽  
pp. 776-792 ◽  
Author(s):  
Madhab Chandra Tripathy ◽  
Debasmita Mondal ◽  
Karabi Biswas ◽  
Siddhartha Sen
Keyword(s):  
Fractional Order ◽  
Phase Locked Loop ◽  
Performance Study ◽  
Loop Filter ◽  
And Performance

Analysis and Design of High Performance Phase Frequency Detector, Charge Pump and Loop Filter Circuits for Phase Locked Loop in Wireless Applications

2016 ◽  
Vol 4 (2) ◽  
pp. 397
Author(s):  
P.N. Metange ◽  
K. B. Khanchandani
Keyword(s):  
Leakage Current ◽  
High Performance ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Loop Filter ◽  
Phase Frequency Detector ◽  
Analysis And Design ◽  
Wireless Applications ◽  
5 Ghz ◽  
Frequency Detector

<p>This paper presents the analysis and design of high performance phase frequency detector, charge pump and loop filter circuits for phase locked loop in wireless applications. The proposed phase frequency detector (PFD) consumes only 8 µW and utilises small area. Also, at 1.8V voltage supply the maximum operation frequency of the conventional PFD is 500 MHz whereas proposed PFD is 5 GHz. Hence, highly suitable for low power, high speed and low jitter applications.  The differential charge pump uses switches using NMOS and the inverter delays for up and down signals do not generate any offset due to its fully symmetric operation. This configuration doubles the range of output voltage compliance compared to single ended charge pump. Differential stage is less sensitive to the leakage current since leakage current behaves as common mode offset with the dual output stages. All the circuits are implemented using cadence 0.18 μm CMOS Process.</p>

An Ultra-Wide Range Digitally Adaptive Control Phase Locked Loop with New 3-Phase Switched Capacitor Loop Filter

2007 ◽  
Vol E90-C (6) ◽  
pp. 1197-1202
Author(s):  
S. DOSHO ◽  
N. YANAGISAWA ◽  
K. SOGAWA ◽  
Y. YAMADA ◽  
T. MORIE
Keyword(s):  
Adaptive Control ◽  
Phase Locked Loop ◽  
Switched Capacitor ◽  
Loop Filter ◽  
Control Phase ◽  
Wide Range

Design of microwave signal source for CS chip-scale atomic clock

2017 ◽  
Vol 31 (07) ◽  
pp. 1741010 ◽  
Author(s):  
Ji Lei ◽  
Meng Hui Zhi ◽  
Xin Wei Li ◽  
Tang Liang ◽  
Dong Hai Qiao
Keyword(s):  
Phase Noise ◽  
Low Temperatures ◽  
Good Condition ◽  
Atomic Clock ◽  
Phase Locked Loop ◽  
Microwave Signal ◽  
Coherent Population Trapping ◽  
Signal Source ◽  
Loop Filter ◽  
High And Low Temperatures

Nowadays, some countries have already invented chip-scale atomic clock (CSAC) based on coherent population trapping (CPT), and it has been applied in every areas. According to its working principle, the microwave signal source is one of the decisive factors affecting its stability. Usually the microwave signal source is a phase-locked loop circuit, it mainly includes a frequency synthesizer, a voltage controlled oscillator (VCO) and a loop filter. This paper aims to develop a microwave signal source for Cs CSAC. First, a VCO should be designed, in order to validate the characteristic of the designed VCO, the VCO needs to be tested at high and low temperatures, and the results show that it has good stability of high and low temperatures. Second, for the purpose of verifying that the design and production consistency of the VCO are in good condition, 1000 VCOs are test, respectively. The statistical distribution of the phase noise at 1 kHz offset would be painted a curve. Finally, the designed VCO (PN: 61.01dBc/Hz@1kHz) will be applied in phase-locked loop, the test results show that the phase noise is −83.57dBc/Hz@300Hz, it is much better than −43dBc/Hz@300Hz which is the spec of CSAC. If the microwave signal source would be used in CSAC, its stability would be greatly improved.

scholarly journals A 4-4.8GHz Adaptive Bandwidth, Adaptive Jitter Phase Locked Loop

2017 ◽  
Vol 7 (2) ◽  
pp. 1473-1477 ◽  
Author(s):  
H. E. Taheri
Keyword(s):  
Pump Current ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Reference Frequency ◽  
Monitor Unit ◽  
Loop Filter ◽  
Loop Bandwidth ◽  
Simulation Results ◽  
Adaptive Bandwidth ◽  
Low Phase Noise

A low power, low phase noise adaptive bandwidth phase locked loop is presented in this paper. The proposed structure benefits from a novel lock status monitor unit (LSMU) that determines loop operation and loop bandwidth. The loop filter resistance and charge pump current are inversely proportional and bandwidth to reference frequency is maintained fixed. This structure is simulated in 0.18 μm CMOS technology and simulation results are presented.

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