Pipelined parallel architecture for high throughput MAP detectors

Advanced Encryption Standard (AES) is the most popular symmetric encryption method, which encrypts streams of data by using symmetric keys. The current preferable AES architectures employ effective methods to achieve two important goals: protection against power analysis attacks and high-throughput. Based on a different architectural point of view, we implement a particular parallel architecture for the latter goal, which is capable of implementing a more efficient pipelining in field-programmable gate array (FPGA). In this regard, all intermediate registers which have a role for unrolling the main loop will be removed. Also, instead of unrolling the main loop of AES algorithm, we implement pipelining structure by replicating nonpipelined AES architectures and using an auto-assigner mechanism for each AES block. By implementing the new pipelined architecture, we achieve two valuable advantages: (a) solving single point of failure problem when one of the replicated parts is faulty and (b) deploying the proposed design as a fault tolerant AES architecture. In addition, we put emphasis on area optimization for all four AES main functions to reduce the overhead associated with AES block replication. The simulation results show that the maximum frequency of our proposed AES architecture is 675.62[Formula: see text]MHz, and for AES128 the throughput is 86.5[Formula: see text]Gbps which is 30.9% better than its closest existing competitor.

Download Full-text

FPGA implementation of AES algorithm for high throughput using folded parallel architecture

Security and Communication Networks ◽

10.1002/sec.651 ◽

2012 ◽

Vol 7 (11) ◽

pp. 2225-2236 ◽

Cited By ~ 20

Author(s):

K. Rahimunnisa ◽

P. Karthigaikumar ◽

Soumiya Rasheed ◽

J. Jayakumar ◽

S. SureshKumar

Keyword(s):

High Throughput ◽

Parallel Architecture ◽

Fpga Implementation ◽

Aes Algorithm

Download Full-text

High Throughput VLSI Architecture of MQ-Coder for JPEG2000

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.403-408.2321 ◽

2011 ◽

Vol 403-408 ◽

pp. 2321-2324

Author(s):

Jiang Yi Shi ◽

Jie Pang ◽

Zhi Xiong Di ◽

Yao Hui Liu ◽

Yun Song Li

Keyword(s):

High Throughput ◽

Clock Cycle ◽

Parallel Architecture ◽

Vlsi Architecture ◽

Bit Plane Coding ◽

Bit Plane

In this paper, a design of high throughput VLSI architecture of MQ-Coder is proposed. Usually, because the regular operation of the MQ-Coder is sequential, the coding speed will be bottlenecked at the interface between the output of the Bit-Plane coding and the input of the MQ-Coder. Therefore, the proposed MQ-Coder architecture can process two symbols for each clock cycle. The main characteristics are the prediction of index, the simplified condition of renormalization, and the partly parallel architecture in renormalization. From synthesis results of the DC tools, using the TSMC 0.18 μm technology library, the frequency can reach 285.4MHz, which is comparable to that of other architectures and suitable for chip implementation.

Download Full-text

High-Throughput, Resource-Efficient Multi-Dimensional Parallel Architecture for Space-Borne Sea-Land Segmentation

Journal of Circuits System and Computers ◽

10.1142/s0218126621500274 ◽

2020 ◽

pp. 2150027

Author(s):

Cunguang Zhang ◽

Hongxun Jiang ◽

Riwei Pan ◽

Haiheng Cao ◽

Mingliang Zhou

Keyword(s):

Remote Sensing ◽

High Throughput ◽

Large Scale ◽

Parallel Architecture ◽

Remote Sensing Image ◽

Satellite System ◽

Peak Performance ◽

Remote Sensing Images ◽

Block Level ◽

Remote Sensing Image Processing

Sea-land segmentation based on edge detection is commonly utilized in ship detection, coastline extraction, and satellite system applications due to its high accuracy and rapid speed. Pixel-level distribution statistics do not currently satisfy the requirements for high-resolution, large-scale remote sensing image processing. To address the above problem, in this paper, we propose a high-throughput hardware architecture for sea-land segmentation based on multi-dimensional parallel characteristics. The proposed architecture is well suited to wide remote sensing images. Efficient multi-dimensional block level statistics allow for relatively infrequent pixel-level memory access; a boundary block tracking process replaces the whole-image scanning process, markedly enhancing efficiency. The tracking efficiency is further improved by a convenient two-step scanning strategy that feeds back the path state in a timely manner for a large number of blocks in the same direction appearing in the algorithm. The proposed architecture was deployed on Xilinx Virtex k7-410t to find that its practical processing time for a [Formula: see text] remote sensing image is only about 0.4[Formula: see text]s. The peak performance is 1.625[Formula: see text]gbps, which is higher than other FPGA implementations of segmentation algorithms. The proposed structure is highly competitive in processing wide remote sensing images.

Download Full-text