High-speed low-power logic gates using floating gates

2003 ◽  
Author(s):  
E. Rodriguez-Villegas ◽  
J.M. Quintana ◽  
M.J. Avedillo ◽  
A. Rueda
Keyword(s):  
Low Power ◽  
High Speed ◽  
Logic Gates ◽  
Floating Gates ◽  
Low Power Logic

High-Speed, Low-Power Logic ICs using Quasi-Normally-Off GaAs MESFETs

1980 ◽  
Author(s):  
G. Nuzillat ◽  
G. Bert ◽  
F. Damay-Kavala ◽  
C. Arnodo
Keyword(s):  
Low Power ◽  
High Speed ◽  
Low Power Logic

scholarly journals Carrier Transport in High-Mobility III–V Quantum-Well Transistors and Performance Impact for High-Speed Low-Power Logic Applications

2008 ◽  
Vol 29 (10) ◽  
pp. 1094-1097 ◽  
Author(s):  
G. Dewey ◽  
M.K. Hudait ◽  
Kangho Lee ◽  
R. Pillarisetty ◽  
W. Rachmady ◽  
...  
Keyword(s):  
Quantum Well ◽  
Low Power ◽  
High Speed ◽  
Carrier Transport ◽  
High Mobility ◽  
Performance Impact ◽  
And Performance ◽  
Low Power Logic

Design and Simulation of Low-Power Logic Gates Based on Nanoscale Side-Contacted FED

2017 ◽  
Vol 64 (1) ◽  
pp. 306-311 ◽  
Author(s):  
Behnam Jafari Touchaei ◽  
Negin Manavizadeh
Keyword(s):  
Low Power ◽  
Logic Gates ◽  
Low Power Logic

scholarly journals Reversible Gate Logic Adder with Parity Preserving Design

2021 ◽  
Vol 1 (2) ◽  
Author(s):  
Kannadasan K
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Error Detection ◽  
High Speed ◽  
Logic Gates ◽  
Digital Circuit ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Main Challenge ◽  
Wide Range

Reversible logic circuits have drawn attention from a variety of fields, including nanotechnology, optical computing, quantum computing, and low-power CMOS design. Low-power and high-speed adder cells (like the BCD adder) are used in binary operation-based electronics. The most fundamental digital circuit activity is binary addition. It serves as a foundation for all subsequent mathematical operations. The main challenge today is to reduce the power consumption of adder circuits while maintaining excellent performance over a wide range of circuit layouts. Error detection in digital systems is aided by parity preservation. This article proposes a concept for a fault-tolerant parity- preserving BCD adder. To reduce power consumption and circuit quantum cost, the proposed method makes use of reversible logic gates like IG, FRG, and F2G. Comparing the proposed circuit to the current counterpart, it has fewer constant inputs and garbage outputting devices and is faster.

Communication—Potential of the π-Gate InAs HEMTs for High-Speed and Low-Power Logic Applications

2019 ◽  
Vol 8 (6) ◽  
pp. P319-P321
Author(s):  
Jing-Neng Yao ◽  
Yueh-Chin Lin ◽  
Ying-Chieh Wong ◽  
Ting-Jui Huang ◽  
Heng-Tung Hsu ◽  
...  
Keyword(s):  
Low Power ◽  
High Speed ◽  
Low Power Logic
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