Multi-valued logic function implementation with novel current-mode logic gates

2003 ◽  
Author(s):  
T. Temel ◽  
A. Morgul
Keyword(s):  
Logic Gates ◽  
Current Mode ◽  
Logic Function ◽  
Current Mode Logic

High-Performance Current-Mode Logic Ternary D Flip-Flop Based on Bipolar Complementary Metal Oxide Semiconductor

2021 ◽  
Vol 16 (4) ◽  
pp. 528-533
Author(s):  
Xianghong Zhao ◽  
Longhua Ma ◽  
Hongye Su ◽  
Jieyu Zhao ◽  
Weiming Cai
Keyword(s):  
High Frequency ◽  
High Speed ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Oxide Semiconductor ◽  
Logic Function ◽  
Flip Flop ◽  
Current Mode Logic ◽  
Transmission Speed

In this paper, a simple-structured and high-performance current-mode logic (CML) ternary D flip-flop based on BiCMOS is proposed. It combines both advantages of BiCMOS and CML circuits, which is with much more high-speed, strong-drive and anti-interference abilities. Utilizing TSMC 180 nm process, results of simulations carried out by HSPICE illustrate the proposed circuit not only has correct logic function, but also gains improvements of 95.6~98.4% in average D-Q delay and 16.2%~70.4 in PDP compared with advanced ternary D flip-flop. When compared at the same information transmission speed, proposed circuit is more competitive. Furthermore, it can perform up to high frequency of 15 GHz and drive heavier load. All the results prove that proposed circuit is high-performance and very suitable for high-speed and high-frequency applications.

scholarly journals MOS Current Mode Logic with Capacitive Coupling

2012 ◽  
Vol 2012 ◽  
pp. 1-7 ◽  
Author(s):  
Kirti Gupta ◽  
Neeta Pandey ◽  
Maneesha Gupta
Keyword(s):  
Analytical Model ◽  
Digital Circuits ◽  
Logic Gates ◽  
Current Mode ◽  
Cmos Technology ◽  
Capacitive Coupling ◽  
Ring Oscillator ◽  
Switching Speed ◽  
Current Mode Logic

A new MOS current mode logic (MCML) style exhibiting capacitive coupling to enhance the switching speed of the digital circuits is proposed. The mechanism of capacitive coupling and its effect on the delay are analytically modeled. SPICE simulations to validate the accuracy of the analytical model have been carried out with TSMC 0.18 μm CMOS technology parameters. Several logic gates such as five-stage ring oscillator, NAND, XOR2, XOR3, multiplexer, and demultiplexer based on the proposed logic style are implemented and their performance is compared with the conventional logic gates. It is found that the logic gates based on the proposed MCML style lower the delay by 23 percent. An asynchronous FIFO based on the proposed MCML style has also been implemented as an application.

Model and Design of Improved Current Mode Logic Gates

2020 ◽  
Author(s):  
Kirti Gupta ◽  
Neeta Pandey ◽  
Maneesha Gupta
Keyword(s):  
Logic Gates ◽  
Current Mode ◽  
Current Mode Logic
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