A new architecture to compute the discrete cosine transform using the quadratic residue number system

2002 ◽  
Author(s):  
J. Ramirez ◽  
A. Garcia ◽  
P.G. Fernandez ◽  
L. Parrilla ◽  
A. Lloris
Keyword(s):  
Discrete Cosine Transform ◽  
Number System ◽  
Residue Number System ◽  
Quadratic Residue ◽  
Cosine Transform ◽  
Residue Number

A Fast QRNS-Based Algorithm for the DCT and Its Field-Programmable Logic Implementation

2003 ◽  
Vol 12 (01) ◽  
pp. 111-123 ◽  
Author(s):  
Javier Ramírez ◽  
Antonio García
Keyword(s):  
Digital Signal ◽  
Number System ◽  
Residue Number System ◽  
Quadratic Residue ◽  
Programmable Logic ◽  
Cosine Transform ◽  
Speed Increase ◽  
Residue Number ◽  
Field Programmable ◽  
Field Programmable Logic

This paper assesses the arithmetic benefits provided by the Residue Number System (RNS) for building Digital Signal Processing (DSP) systems with Field-Programmable Logic (FPL) technology. The quantifiable benefits of this approach are studied in the context of a new Fast Cosine Transform (FCT) architecture enhanced by using the Quadratic Residue Number System (QRNS). The system reduces the number of adders and multipliers required for the N-point Discrete Cosine Transform (DCT) and provides high throughput. For an FPL-based implementation, the proposed design gets significant improvements over an equivalent 2C structure. By using up to 6-bit moduli, an overall increase in the system performance of about 140% is achieved. If this speed increase is considered along with the penalty in device resources, the presented QRNS-based FCT system provides an improvement in the area-delay figure factor of about 20%. Finally, the conversion overhead was carefully studied and it was found that the quantifiable benefits of the proposed design are not affected when converters are included.

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