An efficient scheme based on EMPDC graph model in synthesizing fault tolerant FIR filter

2002 ◽  
Author(s):  
Choon-Sik Park ◽  
M. Kaneko
Keyword(s):  
Fault Tolerant ◽  
Graph Model ◽  
Fir Filter ◽  
Efficient Scheme

FPGA Synthesis of Reconfigurable Modules for FIR Filter

2015 ◽  
Vol 4 (2) ◽  
pp. 63
Author(s):  
Saranya R ◽  
Pradeep C ◽  
Neena Baby ◽  
Radhakrishnan R
Keyword(s):  
Reconfigurable Computing ◽  
Fault Tolerant ◽  
Fir Filter ◽  
Divide And Conquer ◽  
Coarse Grained ◽  
Verilog Hdl ◽  
Detection Mechanism ◽  
Fine Grained ◽  
Dsp Systems ◽  
Important Building Block

Reconfigurable computing for DSP remains an active area to explore as the need for incorporation with more conventional DSP technologies turn out to be obvious. Conventionally, the majority of the work in the area of reconfigurable computing is aimed on fine grained FPGA devices. Over the years, the focus is shifted from bit level granularity to a coarse grained composition. FIR filter remains and persist to be an important building block in various DSP systems. It computes the output by multiplying input samples with a set of coefficients followed by addition. Here multipliers and adders are modeled using the concept of divide and conquer. For developing a reconfiguarble FIR filter, different tap filters are designed as separate reconfigurable modules. Furthermore, there is an additional concern for making the system fault tolerant. A fault detection mechanism is introduced to detect the faults based on the nature of operands. The reconfigurable modules are structurally modeled in Verilog HDL and simulated and synthesized using Xilinx ISE 14.2. A comparison of the device utilization of reconfigurable modules is also presented in this paper by implementing the design on various Virtex FPGA devices.

A novel fault-tolerant control strategy based on inverse bicausal bond graph model in linear fractional transformation

2021 ◽  
Vol 13 (11) ◽  
pp. 168781402110598
Author(s):  
Yacine Lounici ◽  
Youcef Touati ◽  
Smail Adjerid ◽  
Djamel Benazzouz ◽  
Billal Nazim Chebouba
Keyword(s):  
Time Delay ◽  
Control Strategy ◽  
Fault Tolerant ◽  
Graph Model ◽  
Fault Tolerant Control ◽  
Bond Graph ◽  
Pi Controller ◽  
Control Signal ◽  
Linear Fractional Transformation ◽  
Fault Estimation

This article presents the development of a novel fault-tolerant control strategy. For this task, a bicausal bond graph model-based scheme is designed to generate online information to the inverse controller about the faults estimation. Secondly, a new approach is proposed for the fault-tolerant control based on the inverse bicausal bond graph in linear fractional transformation form. However, because of the time delay for fault estimation, the PI controller is used to reduce the error before the fault is estimated. Hence, the required input that compensates the fault is the sum of the control signal delivered by the PI controller and the control signal resulting from the inverse bicausal bond graph for fast fault compensation and for maintaining the control objectives. The novelties of the proposed approach are: (1) to exploit the power concept of the bond graph by feeding the power generated by the fault in the inverse model (2) to suitably combining the inverse bicausal bond graph with the PI feedback controller so that the proposed strategy can compensate for the fault with a very short time delay and stabilize the desired output. Finally, the experimental results illustrate the efficiency of the proposed strategy.

scholarly journals Design of a Fault Tolerant Razor Flip Flop Sklansky Adder for Delay Reduction in FIR Filter

2019 ◽  
Vol 8 (9) ◽  
pp. 2647-2651
Keyword(s):  
Fault Tolerance ◽  
High Performance ◽  
Fault Tolerant ◽  
Digital Signal ◽  
Fir Filter ◽  
Delay Reduction ◽  
Flip Flop ◽  
Multiple Faults ◽  
Fault Tolerant System ◽  
Logic Unit

Basically, to reduce the failure rate in the system, we need to introduce the fault tolerant system. Because of multiple faults occurred in the system, the system will increase the area. To employ the adder architecture, different algorithms are used in digital signal processing. By introducing the fault tolerant system, the reliability of the proposed system will increase. So in this paper we introduced the design of fault tolerant razor flip flop using SKLANSKY adder for delay reduction in FIR filter. The razor flip flop will increase the energy efficiency of proposed system. This flip flop will store the information by latching the circuit. The SKLANSKY adder is the part of arithmetic logic unit. In proposed system, all bits are summed and followed to the fault tolerance system,. This fault tolerance system will detect the error and give efficient output. Hence compared to existed system, the proposed system gives high performance and accuracy in terms of delay.

A fault tolerant oriented CMOS systolic implementation of an FIR filter

1989 ◽  
Vol 25 (1-5) ◽  
pp. 97-105
Author(s):  
G.L. Aranci ◽  
C.A. Binda ◽  
U. Clerici ◽  
E. Comignaghi
Keyword(s):  
Fault Tolerant ◽  
Fir Filter
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